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This article about crystal oscillators talks about the trade-offs of different crystal load capacitance values (crystal load capacitance parameter, not load capacitor values)

It says “a crystal with a lower CL is going to have a faster startup time” and “lower CL means that the negative resistance provided by the oscillator transistor is higher so that the oscillation can be sustained with lower power” … “Given these power advantages, why would anyone choose a higher CL crystal? The answer is frequency stability.”

Then says “if parasitic capacitance changes, which can be modeled as part of Co, the resulting frequency change will be less if CL is large. If a crystal with a low CL is used, small changes in parasitics will cause larger changes in frequency.”

My question is, why would parasitic capacitance change unless you make physical changes to the board?

Additionally, would you say that it is best to always select the crystal with lowest CL if the parasitic capacitance is not expected to change? Or do you have any other thoughts on the matter?

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    \$\begingroup\$ If you add too much load capacitance to a modern tiny crystal, you'll not only end up with an oscillating frequency on the low-side, but you'll likely go over its maximum power limit (not good). \$\endgroup\$
    – glen_geek
    Apr 24, 2021 at 19:23
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    \$\begingroup\$ Crystal loading and frequency uncertainty \$\endgroup\$
    – Andy aka
    Apr 25, 2021 at 8:48

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A parasitic capacitance happens anywhere that there's two conductors and a dielectric. Because a parasitic effect is, by definition, uncontrolled, parasitic capacitances are uncontrolled.

The parasitic capacitances on a circuit board are going to depend on the physical spacing between the conductors involved, and the properties of the dielectrics involved.

In general, the spacing is set by the position of chips and traces, and the dielectrics are chip package material, the board material (i.e., FR-4), and air. You can probably ignore the air and treat it as vacuum, but that leaves other dielectrics.

From board to board, components may end up in slightly different places, because soldering processes are optimized for electronic reliability, not exact placement. The thickness of the board will vary, and the actual trace edges may vary slightly. The material that the board is built out of may vary in dielectric constant, even if it is from the same manufacturer. In addition, the actual components may vary in size and composition from lot to lot, and is almost guaranteed to do so if your product is in production for years.

Over temperature, the dielectric constant and size of your board material will change, as will the dielectric constant and placing of the leads on your chip and crystal holder. Similarly, humidity may cause dimensional changes in most materials, and a board that is subject to vibration may undergo dimensional changes either over a period of vibration, or permanently as pieces bend.

All of this means that your parasitic capacitances will change from board to board and over temperature. If you're good at board design, you can minimize the parasitic capacitances -- and, hence, the change they undergo -- but this ends up being a bit of a black art, and you're still only minimizing them, not making them go away.

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The stray capacitances happen in parts of the system that are largely unavoidable structures, such as PCB wiring.

These can be affected by moisture from humidity, thermal expansion or just from residual flux or other dirt like dust particles. Even the glass fiber weaving can be at different offset between boards so these are not fixed values.

Therefore the crystal with highest load capacitance rating has the least change in frequency due to variations in the parasitic capacitance.

But it may not always be the best to select a crystal with highest or lowest CL rating. The oscillator should be given a crystal it works best with, so looking simply at CL rating will not work. There is also sometimes certain ESR and shunt capacitance ratings, and sometimes oscillator suggests a crystal with certain CL rating. The crystal lattice cut direction may also be important as well as the initial tolerance and temperature tolerance curve given certain temperature range limits.

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