Verilog offers three system tasks related to the simulation timestep:
$time returns the current time as a 64-bit integer, in units of the timestep defined by the `timescale directive.
$stime returns the same value as a 32-bit integer.
$realtime returns the same value as a real number.
However none of these system directives are likely to be useful for synthesis. They would normally be implemented by special code in the simulator that accesses variables in the simulator program.
To keep track of time in a real circuit, you need to start with an input clock with a known frequency. For good accuracy you'd generate this with a crystal oscillator circuit, which would be entirely outside your device if you're working on an FPGA.
Then you simply build a counter to keep track of ticks of your clock (note code not tested):
module time_counter(input clk, input rst, output reg [31:0] ticks)
always @(posedge clk or posedge rst) begin
if (rst) begin
ticks <= 32'h00000000;
ticks <= ticks + 1;
There is a limit to how fast a counter like this can operate, and various tricks to build faster counters if needed.
If you need to find the period of an input with an unknown period, you need to compare it to a clock with a known period. It's simplest conceptually to make the known clock much faster than the unknown clock and count ticks of the known clock for each period of the unknown clock. If that's not possible, you can divide the unknown clock by some factor (say 16 or 128 or 1024) and count ticks of the known clock for each cycle of the divider to work out the unknown period.