# Cascaded flip-flops and shift register timing

In the D-flip flop at the edge triggering of the clock, $$\Q(t+1)=D\$$.

In the figure below, shift-register using cascaded flip flops, why don't we assume that at clock edge triggering $$\Q_1(t+1)=D_1\$$ and $$\Q_2(t+1)=D_2=Q_1(t+1)\$$...etc. so $$\Q_4(t+1)=Q_3(t+1)=Q_2(t+1)=Q_1(t+1)=D_1\$$?

Is the propagation delay what makes the schematic below a shift register? How can I put that into consideration? • May as well add this from EESE. It's related.
– jonk
Apr 25 at 18:32

To understand it, consider first a gated D-Latch which is level sensitive which means that the input is applied to the output as long as the gate (E) is active, otherwise the last state is maintained: Now one way to implement an edge triggered D-FlipFlop is by using two D-Latches in a master-slave configuration: When the clock is low the first latch (the master) is activated and its output follows the D input but the second latch (slave) retains its last state.

When the clock switches to 1, the master holds the state available at the rising edge and then the slave will be active and its output follows the maintained output of the master. This value will remian until the next clock edge.

Now if you consider the successive D-FlipFlops of your circuit:

• Before the clock rising edge, the master of each Flipflop is connected to the state held by the slave of the previous Flipflop at the previous clock edge .
• At the rising edge of the clock, it is this maintained value that will be latched by the master of each Flipflop which is the status at the previous clock edge. this maintained value will be applied to the output of the D-Flipflop after the rising edge.
• Well, you just invalidated some of what I was writing. So out that goes. +1 for the addition that improves on the answer by Math Keeps Me Busy.
– jonk
Apr 25 at 6:45
• The circuit for a D-Flip-Flop may work for a single integrated circuit, but it relies upon propagation delays being carefully controlled. May not work with individual components, and definitely does not pass digital verifiers. Apr 25 at 14:18
• @MathKeepsMeBusy I said it may be implemented like that. I have chosen that circuit just to make it easy to understand. Anyway I will not discuss the performence of such a circuit in a comment. Apr 25 at 14:27
• @MathKeepsMeBusy You are correct, the delays must be carefully controlled. Real flip-flops are designed with a lot of SPICE simulations over the full range of temperature, voltage, and process variation. It's entirely possible that the hold time or setup time for such a flip-flop could be zero or negative, depending on the relative delays in the clocking and data input paths. Apr 25 at 17:55
• Thanks, they are nicely done! Apr 25 at 22:11

Edge triggered FFs have set-up and hold time requirements. Only data that was present before the clock triggered, will have satisfied the set-up time, and thus be "registered". Since (if well designed) the FFs have their clocks triggered at the same time, or nearly the same time, data that is "registered" at the input of one FF will appear at that FF's output too late to be registered by the next FF. That is why changes that happen in one FF don't just ripple down the entire shift register in one clock cycle. 