# Cascaded flip-flops and shift register timing

In the D-flip flop at the edge triggering of the clock, $$\Q(t+1)=D\$$.

In the figure below, shift-register using cascaded flip flops, why don't we assume that at clock edge triggering $$\Q_1(t+1)=D_1\$$ and $$\Q_2(t+1)=D_2=Q_1(t+1)\$$...etc. so $$\Q_4(t+1)=Q_3(t+1)=Q_2(t+1)=Q_1(t+1)=D_1\$$?

Is the propagation delay what makes the schematic below a shift register? How can I put that into consideration?

• May as well add this from EESE. It's related.
– jonk
Apr 25 at 18:32

To understand it, consider first a gated D-Latch which is level sensitive which means that the input is applied to the output as long as the gate (E) is active, otherwise the last state is maintained:

Now one way to implement an edge triggered D-FlipFlop is by using two D-Latches in a master-slave configuration:

When the clock is low the first latch (the master) is activated and its output follows the D input but the second latch (slave) retains its last state.

When the clock switches to 1, the master holds the state available at the rising edge and then the slave will be active and its output follows the maintained output of the master. This value will remian until the next clock edge.

Now if you consider the successive D-FlipFlops of your circuit:

• Before the clock rising edge, the master of each Flipflop is connected to the state held by the slave of the previous Flipflop at the previous clock edge .
• At the rising edge of the clock, it is this maintained value that will be latched by the master of each Flipflop which is the status at the previous clock edge. this maintained value will be applied to the output of the D-Flipflop after the rising edge.
• Well, you just invalidated some of what I was writing. So out that goes. +1 for the addition that improves on the answer by Math Keeps Me Busy.
– jonk
Apr 25 at 6:45
• The circuit for a D-Flip-Flop may work for a single integrated circuit, but it relies upon propagation delays being carefully controlled. May not work with individual components, and definitely does not pass digital verifiers. Apr 25 at 14:18
• @MathKeepsMeBusy I said it may be implemented like that. I have chosen that circuit just to make it easy to understand. Anyway I will not discuss the performence of such a circuit in a comment. Apr 25 at 14:27
• @MathKeepsMeBusy You are correct, the delays must be carefully controlled. Real flip-flops are designed with a lot of SPICE simulations over the full range of temperature, voltage, and process variation. It's entirely possible that the hold time or setup time for such a flip-flop could be zero or negative, depending on the relative delays in the clocking and data input paths. Apr 25 at 17:55
• Thanks, they are nicely done! Apr 25 at 22:11

Edge triggered FFs have set-up and hold time requirements. Only data that was present before the clock triggered, will have satisfied the set-up time, and thus be "registered". Since (if well designed) the FFs have their clocks triggered at the same time, or nearly the same time, data that is "registered" at the input of one FF will appear at that FF's output too late to be registered by the next FF. That is why changes that happen in one FF don't just ripple down the entire shift register in one clock cycle.

The design of an edge triggered D-Flip-Flop used in another answer (by Paul Ghobril), and shown here, may work in an integrated circuit, but relies upon careful control of propagation delays. That is, it is susceptible to race conditions. (Sadly it is found all over the internet).

A edge triggered D-Flip-Flop that does not depend upon careful control of propagation delays is this:

• That's not really correct, you don't just hope that propagation delay for the data will be slower than the propagation delay for the clock signal. I assume that in OP's context these are not transparent latches but actual flip-flops. What you're describing would apply to the former and it would not be a good idea to depend on that kind of behaviour. Apr 25 at 13:59
• @ToddSewell. I didn't "hope that propagation delay for the data will be slower than the propagation delay for the clock signal." I said that the set-up time will not be met. It cannot be met, (unless it is negative!) "I assume that in OP's context these are not transparent latches" The little triangle at the Data Input indicates edge triggered. Apr 25 at 14:13
• @PaulGhobril You posted your figure in an answer. I think that makes it fair-use. I will let moderators decide whether it can be used. Apr 25 at 14:34
• @PaulGhobril - Hi, It isn't a moderator decision, but something that we all agree to in the Ts & Cs of the site. See here sections 5 & 6, for example: "Please note that any content or information you share publicly is governed by the terms described below in the section titled “Content Permissions, Restrictions, and Creative Commons Licensing,” and you should be aware that once you place content in the public sphere, you willingly give up some rights and control over such content.". So yes, Math can include your images, with attribution. Apr 25 at 14:44
• MathKeepsMeBusy - Hi, In this case, I believe that by being placed in an answer, the image has been perpetually licensed to SE. Therefore linking to it, with attribution as you have done, complies with the page I linked above. That's my best interpretation of the rules. || Please keep any disagreements civil (as they seem to be so far, thanks to you and @PaulGhobril for that), and if they are not technical, please take them to chat (or, if there is a non-legal meta question, it can be asked on Electrical Engineering Meta). Any legal questions should go to SE, via the "Contact" link at the bottom of the page. Apr 25 at 15:01