RAM (Random Access Memory) fully decodes the address to select one data unit (word) from the data array, using multiplexer and demultiplexer logic to steer the data path to the right word. RAM has an address granularity of one data word. True RAM has the lowest possible latency and least amount of overhead per access.
The exact structure of the RAM will depend on its size, with simple RAMs using a straight address-to-word decode into a linear storage array, while larger RAMs will use multiple arrays in compound 2-d arrangements designed to minimize logic, improve speed, and improve scalability through using pre-defined RAM arrays.
More here: https://ece.uwaterloo.ca/~mhanis/lecture/sram.pdf
This differs from block or sequential memories, that work with larger data units and/or don’t fully decode the address. With these types of memory, you will have to shuffle through some larger chunk of data to ultimately get to the word you need.
DRAM for example isn’t truly random, but is block-oriented. These blocks are called rows, which in turn are buffered into columns by a local on-chip RAM. DRAM data I/O occurs in bursts of 4 to 8 words depending on the DRAM type, using the column index as the starting point into the embedded column RAM.
This row-column-burst arrangement adds extra overhead for each DRAM transaction, so systems using DRAM try to arrange accesses to avoid row-change overhead. Nevertheless, DRAM used with cache RAM offers very high performance.
Flash memory is block-oriented internally, and has a minimum access unit of one block (128KB typically.) Like DRAM, Flash uses RAM to buffer I/O transactions, and there’s an even bigger penalty crossing from block to block than DRAM.
An example of a sequential memory is the hard disk. Data are transferred to or from the platters in order, and - you guessed it - buffered into blocks using RAM as part of the controller. Hard disk block size is somewhat arbitrary, depending on the RAM size and how the controller is set up to use it; 512 bytes and 4K bytes are typical.
The hard disk’s non-sequential access overhead is much bigger than for Flash or DRAM (many milliseconds vs. micro- or nanoseconds for Flash or DRAM), owing to both the rotational latency and track-to-track latency. So the host goes to great pains to optimize disk I/O to avoid moving the head (that is, avoid seek operations) and thus keep the I/O operations (IOPs) rate as high as possible.
And finally, we come to a surviving example of truly sequential memory: tape. Tape data are accessed in a strictly linear fashion, and the penalty for non-sequential access can be extreme: many, many seconds if a long seek is needed. If the data are spread across multiple physical tapes (volumes) that seek penalty can be half a minute to multiple minutes. Tape accesses are buffered using disk, flash or DRAM to hide some of this overhead.
In the past there were shift-in / shift-out type memories where you had to wait for your data to 'come around'. Some famous ones include mercury delay lines (1950s) and Intel's abortive 'bubble' memory (1970s) that, in their era, offered better density than contemporary RAM, but had a sequential, shift-in shift-out access model. Neither lasted very long, as RAM, DRAM and disk rapidly became more cost-effective and convenient to use.