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This is a comment that I saw in another forum:

Like any other memory storage, it's divided into smaller units. These units can contain data individually or can be treated as a big single block of memory. So suppose your RAM is divided into 512 individual blocks. You need to access the 199th block. So a sequential approach is to start from one end of the memory and move towards the desired block. So if you started at the 1st block, you need to pass through 1,2,3,4,5,……,197,198 blocks before reaching the desired block no. 199. But Random Access means that instead of passing through all the blocks present between you and the destination, You can directly access the desired block. Thus the time required to read any particular block remains constant regard less of its number, that is its relative position in the chip. Hence, you can access any block in same amount of time as any other block. For example, you can access any of the 512 blocks in exactly same amount of time.

So, starting from that statement, I would like to know exactly how the RAM locates, for example, position 1000 (or any 'position X' that the CPU has indicated) in the same time that it can locate position 1.

I imagine it as a matrix but I can't figure out how it can access exactly to position 1000 without having to go through the other positions. How is this position calculated exactly?

In conclusion, I would like to know how to directly access a memory location without going through the other locations.

Thank you very much in advance.

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  • \$\begingroup\$ By decoding the memory address and accessing it directly. But memory comes in all kinds of forms so there are also memories that cannot give you a single byte at some location, but a larger block from which you need to read the single byte you want. \$\endgroup\$
    – Justme
    Apr 25 '21 at 17:33
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    \$\begingroup\$ There's a selection circuit for each row and each column and the circuits work in parallel to select a row and a column in constant time. It might be more detail than you want, but I reverse-engineered a 16-kilobit RAM chip and explain what's happening internally: righto.com/2020/11/reverse-engineering-classic-mk4116-16.html \$\endgroup\$ Apr 26 '21 at 3:49
  • \$\begingroup\$ nandgame.com is a good way of learning about computer fundamentals \$\endgroup\$ Apr 26 '21 at 10:40
  • \$\begingroup\$ Build an 8-bit computer from scratch : Random access memory (RAM) module \$\endgroup\$
    – J...
    Apr 26 '21 at 16:17
  • \$\begingroup\$ As an aside, a very different approach is content-addressable memory, used in network routers where performance requirements are particularly high. It’s a bunch of modules on a bus, the controller puts a network address on the bus and the module which knows the routing for it responds, as opposed to using regular RAM where the CPU would have to query memory locations one by one to find the right data. \$\endgroup\$ Apr 26 '21 at 22:20
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enter image description here

Figure 1. An 8-bit wide random access memory. Image source: ETSU.

Steps:

  • Select the address to be read. This is binary coded and fed into the memory address decoder.
  • The address decoder selects one row of memory.
  • That row of memory is connected to the databus and outputs a low (0) or high (1) voltage signal on each line.

The diagram alludes to some additional logic such as read/write (to tell whether to put data out on the address lines or to write the contents of the address lines into that memory row) and "chip select" which would be used when more than one memory chip is used.

I imagine it as a matrix but I can't figure out how it can access exactly to position 1000 without having to go through the other positions. How is this position calculated exactly?

The position isn't calculated. It is selected. In your example of reading address 1000 you will need at least a 10-bit address bus (which gives 210 = 1024 addresses). 100010 = 11111010002 so the address lines would be set to that binary address, the address decoder will immediately select row 1000 and put the data out on the data bus. Any address can be read at the same speed. (High addresses do not take longer to access or read.)


enter image description here

Figure 2. A 3-to-8 decoder enables the output (Y) selected by the binary address code (X0 to X2). The logic is arranged so that only one output is on for any input combination. Image source: Codestall.

Obviously, a 10-bit addressing scheme would require a correspondingly large decoder.

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  • \$\begingroup\$ Thanks for your great response. I see it much clearer, but I have a small doubt. In that immediate selection, what happens? I mean how does the memory immediately see that the memory position corresponds to the memory address that the cpu wants to access? In this case, it would not make an immediate addition? always starting from the beginning and adding the rest, that is, in this example 1 + 999 = 1000 all this in binary. So I understand that time is always just as fast. \$\endgroup\$ Apr 25 '21 at 22:16
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    \$\begingroup\$ Have a look at the internal logic of a three to eight decoder and figure out how it works. Then scale it up to as many address lines as you want. \$\endgroup\$
    – Transistor
    Apr 25 '21 at 22:27
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RAM is effectively stored as a 2-dimensional array. Each row in the array would be one address, each column would be one bit of the required word (modern microprocessors may be able to read 8, 16, 32 or 64 bit words at a time).

The microprocessor will put out the desired address on the address bus. A bunch of logic gates will select which memory module is responsible for that address. Then within the memory module, the address will be decoded by more logic gates to select one row of memory. The data bits at that row will be sent to the data bus, to be read by the microprocessor.

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I just want to supplement the great answers explaining how RAM is addressed by the fact that the expression RAM is more a relic of older times. Today almost all memory we use behaves like RAM, at least all solid state memory (flash memory in your SSD, for example, is addressed pretty much the same as your actual RAM).

The term comes from times with magnetic tape storage (similar to the old audio tapes). You application code started at the beginning of the tape. As long as you just read the code consecutively the tape can uniformly move forward and access time is constant. But if you want to jump to another part of the memory (e.g. to call a function or read some data) the tape had to fast forward to that point and skim over all the other data in between these two locations on the tape.
In comparison to that, the term RAM actually makes a lot of sense. The address decoding and accessing via a matrix-structure of modern memory makes it pretty much constant access time, regardless of which block you want to read or write.

Magnetic hard drives (HDDs) as we still use them as mass storage behave like something in between. When accessing another sector the read/write head has to physically move to the new position. A sector nearer the current position is accessed a bit faster than a sector further away, but the read/write head does not have to skim over all memory sections in between.

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    \$\begingroup\$ In case you weren't around in the 1970s, check out Bubble memory which was going to be BIG! Read that and you'll appreciate your RAM all the more. \$\endgroup\$
    – Transistor
    Apr 26 '21 at 14:42
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RAM (Random Access Memory) fully decodes the address to select one data unit (word) from the data array, using multiplexer and demultiplexer logic to steer the data path to the right word. RAM has an address granularity of one data word. True RAM has the lowest possible latency and least amount of overhead per access.

The exact structure of the RAM will depend on its size, with simple RAMs using a straight address-to-word decode into a linear storage array, while larger RAMs will use multiple arrays in compound 2-d arrangements designed to minimize logic, improve speed, and improve scalability through using pre-defined RAM arrays.

More here: https://ece.uwaterloo.ca/~mhanis/lecture/sram.pdf

This differs from block or sequential memories, that work with larger data units and/or don’t fully decode the address. With these types of memory, you will have to shuffle through some larger chunk of data to ultimately get to the word you need.

DRAM for example isn’t truly random, but is block-oriented. These blocks are called rows, which in turn are buffered into columns by a local on-chip RAM. DRAM data I/O occurs in bursts of 4 to 8 words depending on the DRAM type, using the column index as the starting point into the embedded column RAM.

This row-column-burst arrangement adds extra overhead for each DRAM transaction, so systems using DRAM try to arrange accesses to avoid row-change overhead. Nevertheless, DRAM used with cache RAM offers very high performance.

Flash memory is block-oriented internally, and has a minimum access unit of one block (128KB typically.) Like DRAM, Flash uses RAM to buffer I/O transactions, and there’s an even bigger penalty crossing from block to block than DRAM.

An example of a sequential memory is the hard disk. Data are transferred to or from the platters in order, and - you guessed it - buffered into blocks using RAM as part of the controller. Hard disk block size is somewhat arbitrary, depending on the RAM size and how the controller is set up to use it; 512 bytes and 4K bytes are typical.

The hard disk’s non-sequential access overhead is much bigger than for Flash or DRAM (many milliseconds vs. micro- or nanoseconds for Flash or DRAM), owing to both the rotational latency and track-to-track latency. So the host goes to great pains to optimize disk I/O to avoid moving the head (that is, avoid seek operations) and thus keep the I/O operations (IOPs) rate as high as possible.

And finally, we come to a surviving example of truly sequential memory: tape. Tape data are accessed in a strictly linear fashion, and the penalty for non-sequential access can be extreme: many, many seconds if a long seek is needed. If the data are spread across multiple physical tapes (volumes) that seek penalty can be half a minute to multiple minutes. Tape accesses are buffered using disk, flash or DRAM to hide some of this overhead.

In the past there were shift-in / shift-out type memories where you had to wait for your data to 'come around'. Some famous ones include mercury delay lines (1950s) and Intel's abortive 'bubble' memory (1970s) that, in their era, offered better density than contemporary RAM, but had a sequential, shift-in shift-out access model. Neither lasted very long, as RAM, DRAM and disk rapidly became more cost-effective and convenient to use.

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