Your question doesn't include any PCB layout visuals, which is usually the exacerbator of EMI issues, not schematics (although an absence of termination - source or destination - can often be the root cause). Until then, most answers here can't be much more than a stab in the dark (see above), or hand-wavy generalities (see within ;).
I think you have two separate problems here; the 65 & 195MHz on the TTL side, and the ringing on the LVDS side.
You're measuring energy escaping from your board, particularly at the 3rd harmonic (though your plots are zoomed way in, so we can't see what the comparative intensity of the fundamental or higher-order harmonics is).
"High speed" isn't just about the signal's switching frequency, but also about its rise/fall-time. If 3x (195MHz) is your main culprit, this is clearly driven by rise/fall-time, not clock-speed, thus transmission line characteristic impedance, and probably termination thereof - or a lack of it - is the cause.
Like great plane crash disasters, it's rarely just one thing that brings you down, but a combination of things.
Judging by the distance between LCD_CLK & the nearest GND on J1/BONEP8 - aka loop area - the high-order harmonics are probably escaping mostly that way.
So what's under this LCD_CLK track (gnd plane), what's its return path? IOW, how much area is there between LCD_CLK & GND? Do you have a broken GND plane (don't do that) between LCD_CLK's source & destination that's forcing the LCD_CLK's return-path to be deviated around the broken GND plane?
What's the GND on the J1/BONE8 header closest to LCD_CLK? That's a bit of a rhetorical question, we can see there's GNDs all and only up the far end, so that's a problem (especially with a chunky 0.1"-pitch header!). So even if you have a solid unbroken GND plane from the J1/BONEP8 header to under U1, you've still got a loop (in 2 or 3 dimensions) as it hops over J1 from the Bone to your board.
reduce ALL the LCD_x signal's slew rates, if you can configure that (minimises the intensity of the source of the problem).
reduce ALL the LCD_x signal's drive-current, if you can configure that (minimises the intensity of the source of the problem).
if you have a break in your board's GND plane, fix that. deliberate breaks/segmentation of GND planes almost always causes problems, especially if you have control over where things are laid out to control return current flows in the first place.
If that doesn't help (enough), then characteristic impedance termination at source or destination is likely necessary, to reduce the intensity of those high-order harmonics. Because you're using a 'Bone, you don't have the option to put in source-termination, so all you can do is put an RC filter at the destination end, right beside U1.31. Filter values will be determined by how closely your LCD_x signal's track & GND plane geometry (transmission line characteristic impedance) match the source impedance (Beagle's GPIO), so you'll have to research that with the specifics of your situation.
Assuming I'm right, that the source of your problem is rise/fall-time creating strong higher harmonics encountering impedance mismatches along the way, and escaping via a undesirably large loop-area as it goes over J1 & J2, then your problem isn't only LCD_CLK, but all of those LCD_X signals (although they're switching less frequently, each time they do they generate noise), it's just that LCD_CLK is the one that sticks out the most; evidence of this is visible in your 'scope plots, and can be further confirmed by seeing those smaller spikes move to other frequencies as the content of your video output changes). Whether that's enough to cause you to ultimately fail EMC can't be gleaned from your question (application, applicable emissions limits, system-level considerations, etc).
despite the point above, if LCD_CLK is your primary problem (on the TTL side), if you have the opportunity to move LCD_CLK to a different GPIO pin (sorry I'm not familiar enough with the OMAPs to know), one that's closer to a GND on J1/J2, then you'll substantially close that loop-area and have less EMC-compliance-busting energy escaping.
You say you've got ringing on the diff-pair line(s)? That means you've got some of your diff-pair's signal bouncing back from the panel, which means you've got impedance mis-match somewhere along that transmission line between the LVDS-out pins of U1, & the panel's LVDS-receiver chip.
Without knowing anything else about the system (panel, what it's destination diff-pair terminators are, what the characteristic impedance of the LVDS-cable is, what connectors you're using, etc etc etc), it's impossible to dive in further.