How to filter a LVDS clock properly

Question

I have an LCD interface for a Beaglebone Black that is failing EMC. The Pixel clock is 65 MHz and is failing there as well as 195 MHz. Here is what the schematic looks like:

The setup is 24 bits RGB that is converted to LVDS, which there are 4 lanes of data and the differential clock. I found the input LCD clock from the beaglebone to the LVDS transmitter was the worst, especially at 195 MHz. I greatly reduced the EMI by putting in a LC filter (BLM21BB201SN1D with a 22 pF Cap). Here is what it looked like before (195 MHz at center):

After:

The clock integrity was unaffected and this likely would be enough to pass. However, there is still a lot of ringing on the LVDS clock side and I would like to improve it. I tried putting in the same LC filter for the clock but it just impeded the clock too much. I was thinking of adding a common mode filter between the + and - clock but not sure that is the best way filter it. Any thoughts on how to do this would be appreciated.

Edit 1: Adding pictures of layout

Answer 1

Probably what is happening is there is intra-pair skew between the clock line pair lines. Any imbalance in the pair has to make its way back via ground or any of the other connected signals as common-mode noise. This is true of the other pairs as well.

A common-mode filter on the clock will definitely help (as it will with the other signals too.) There’s a whole product category of 0402-sized CM filters designed for HDMI that can be used for this.

Could also try an overall ferrite clamp-on filter for the cable.

Answer 2

Your question doesn't include any PCB layout visuals, which is usually the exacerbator of EMI issues, not schematics (although an absence of termination - source or destination - can often be the root cause). Until then, most answers here can't be much more than a stab in the dark (see above), or hand-wavy generalities (see within ;).

I think you have two separate problems here; the 65 & 195MHz on the TTL side, and the ringing on the LVDS side.

TTL side: You're measuring energy escaping from your board, particularly at the 3rd harmonic (though your plots are zoomed way in, so we can't see what the comparative intensity of the fundamental or higher-order harmonics is).

"High speed" isn't just about the signal's switching frequency, but also about its rise/fall-time. If 3x (195MHz) is your main culprit, this is clearly driven by rise/fall-time, not clock-speed, thus transmission line characteristic impedance, and probably termination thereof - or a lack of it - is the cause.

Like great plane crash disasters, it's rarely just one thing that brings you down, but a combination of things.

Judging by the distance between LCD_CLK & the nearest GND on J1/BONEP8 - aka loop area - the high-order harmonics are probably escaping mostly that way.

So what's under this LCD_CLK track (gnd plane), what's its return path? IOW, how much area is there between LCD_CLK & GND? Do you have a broken GND plane (don't do that) between LCD_CLK's source & destination that's forcing the LCD_CLK's return-path to be deviated around the broken GND plane?

What's the GND on the J1/BONE8 header closest to LCD_CLK? That's a bit of a rhetorical question, we can see there's GNDs all and only up the far end, so that's a problem (especially with a chunky 0.1"-pitch header!). So even if you have a solid unbroken GND plane from the J1/BONEP8 header to under U1, you've still got a loop (in 2 or 3 dimensions) as it hops over J1 from the Bone to your board.

Possible solutions:

• reduce ALL the LCD_x signal's slew rates, if you can configure that (minimises the intensity of the source of the problem).

• reduce ALL the LCD_x signal's drive-current, if you can configure that (minimises the intensity of the source of the problem).

• if you have a break in your board's GND plane, fix that. deliberate breaks/segmentation of GND planes almost always causes problems, especially if you have control over where things are laid out to control return current flows in the first place.

• If that doesn't help (enough), then characteristic impedance termination at source or destination is likely necessary, to reduce the intensity of those high-order harmonics. Because you're using a 'Bone, you don't have the option to put in source-termination, so all you can do is put an RC filter at the destination end, right beside U1.31. Filter values will be determined by how closely your LCD_x signal's track & GND plane geometry (transmission line characteristic impedance) match the source impedance (Beagle's GPIO), so you'll have to research that with the specifics of your situation.

• Assuming I'm right, that the source of your problem is rise/fall-time creating strong higher harmonics encountering impedance mismatches along the way, and escaping via a undesirably large loop-area as it goes over J1 & J2, then your problem isn't only LCD_CLK, but all of those LCD_X signals (although they're switching less frequently, each time they do they generate noise), it's just that LCD_CLK is the one that sticks out the most; evidence of this is visible in your 'scope plots, and can be further confirmed by seeing those smaller spikes move to other frequencies as the content of your video output changes). Whether that's enough to cause you to ultimately fail EMC can't be gleaned from your question (application, applicable emissions limits, system-level considerations, etc).

• despite the point above, if LCD_CLK is your primary problem (on the TTL side), if you have the opportunity to move LCD_CLK to a different GPIO pin (sorry I'm not familiar enough with the OMAPs to know), one that's closer to a GND on J1/J2, then you'll substantially close that loop-area and have less EMC-compliance-busting energy escaping.

LVDS side: You say you've got ringing on the diff-pair line(s)? That means you've got some of your diff-pair's signal bouncing back from the panel, which means you've got impedance mis-match somewhere along that transmission line between the LVDS-out pins of U1, & the panel's LVDS-receiver chip.

Without knowing anything else about the system (panel, what it's destination diff-pair terminators are, what the characteristic impedance of the LVDS-cable is, what connectors you're using, etc etc etc), it's impossible to dive in further.

Answer 3

Keep in mind: You are having problem with a small circuitry, and every small things matter.

1. Adding "extra" filtering on signal lines is the last step, though it is the first choice to attempt for it feels easy. And, you just cannot ignore that sure losing signal margin.

2. SN75LVS83 inputs likely have 50 ohms impedance. While there is no impedance consideration in your circuitry. When the traces are getting long, it becomes significant factor. Though you said it is "ringing", make sure it is not from the impedance matching problem. I am loosely stating this, because the "ringing" has to be addressed first. Following is the remedies to put the ringing (generally, "noise due to signal") under control.

3. Design

(a) Separate VCC, IOVCC, PLLVCC, LVDSVCC. Generously use L&C LPF for isolation. R&C LPF works as fine as L&C. Bulk caps in "0.01 + 0.1 + 1uF" does not do anything (I promise :-)) for the purpose as in your circuitry.

(b) & (c) Add decoupling & Bulk caps here. No bulk caps are needed around the device pins.

3. Layout

(1) A very example of un-tuned antenna. Try to shorten, balance, guard, shield, match impedance, all or as much as you can.

(2) Data lines are in sync with the clock as well. Thus they sing in harmony with the clock, helping clock to emphasized the noise. Apply the same strategy as the clock signal.

(3) These area, other power entry point as well, is where the bulk caps go.

(4) You are wasting capacitors here. Be mindful. We are running into huge problems with part shortage globally. :-)
Do as instructed in the (a), and only one capacitor is enough, I would go with 0.01uF.
The key is, how you construct and control the current path, both the VCC/VDD and GND. That is the art of the decoupling. Whatever you do, place the cap right next to the device pin. I had good result by placing the caps on the solder side, right underneath the device pin. "See" every mills of distance as a circuit, that passing current.

(5) Fill the blank area with copper-pour. It does not cost at all, but, is an effective way to pickup extra emissions.

(6) Good Luck, and let us know how your progress goes.