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I have finished my PCB Design, but I have some doubts about polygons. The stack layer is: Top, GND, PWR and Bottom. On PWR layer I have created 4 polygons for 4 different voltages (5, 3.3, 3.3VDDA and 1.1 V). The brown layer is GND (the down black box is for Raspberry Antenna) and blue layer is PWR. The GND layer is one polygon. Is that the way to that?

I had to connect one component by trace because I couldn't expand the polygon through all the pcb for one component).

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EDIT: The PCB is a Raspberry Compute Module 4 Carrier with an USB 3.0 Controller, with SuperSpeed Signals.

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  • \$\begingroup\$ Could you tell us a bit about the board - which components are on it, what is it supposed to do? Enrico gave you an high-effort worst-case answer, but its very likely this is not needed at all. \$\endgroup\$
    – asdfex
    Apr 27, 2021 at 9:20
  • \$\begingroup\$ @asdfex Sorry, edited. As he tells to me, I'm using a lot of vias connecting the components to ground. If my PCB will have SuperSpeed signals I supose that It will good idea adding grounds planes on all the layers, won't it? Thank you so much! \$\endgroup\$
    – Juanma
    Apr 27, 2021 at 10:02

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You shouldn't use polygons for this purpose.

Use power planes for ground and power, and split the power plane (draw the cut lines) for the various voltages, then assign nets to each part of the power plane.

That way you'll have almost continuous copper on each side, and if you did your layout well, all or most of each power supply rail will lie within one contiguous area of the power plane.

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  • \$\begingroup\$ Thank you so much for your answer Spehro, I have followed a Texas Instruments Layout Guide and they say this: "Never route signals over splits in their perspective reference planes". If I add split planes I have to change the traces of bottom layer to avoid the split planes, isn't it? \$\endgroup\$
    – Juanma
    Apr 27, 2021 at 10:56
  • \$\begingroup\$ I suggest watching this video from Rick Hartley, especially since you have some fairly high frequency signals. \$\endgroup\$
    – Spehro Pefhany
    Apr 27, 2021 at 11:13
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    \$\begingroup\$ Solved, I'm using power planes instead polygons. For avoid routing over splits in their perspective reference planes I shouldn't route over the space between planes, right? Thank you so much! \$\endgroup\$
    – Juanma
    Apr 27, 2021 at 14:57
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I would complete the PCB routing this way:

  1. PCB Grounding

Fill the empty areas of PWR, TOP, and BOTTOM layers, with copper connected to the GND layer. Use many stiching vias all over the board connected to the GND layer.

See this picture. It's full of stiching vias:

enter image description here

  1. PCB copper cage for containing RF spurious emissions caused by fast raising and falling edges currents.

Add a copper border all around the board. Add stiching vias connected to the GND layer all around this border with a step of 2.5 mm.

See this:

enter image description here

Stiching vias can be big. Example: drill 0.4 or 0.3 mm, copper pad diameter 0.7 or 0.8 mm.

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