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I am about to make a revision of a PCB that has 60 mills of Intra-Pair Skew in PCI-E (Gen 2) RX differential pair:

enter image description here

Considering the capacitors the skew is ~50 mills:

enter image description here

this is the relevant part of the stack up for my question:

![stackup pic 1][3]][3

the traces are on layer 1, and the chip is on bottom layer (overall 6 layers) . the traces have 85 Ohm impedance.

Looking in Wikipedia, I learned that for 5 GT/s (Gen 2) the limit is 8 ns skew. how can I approximate if the 60 mills skew are critical in my case?

since the layout is so dense, I can barely do anything to minimize the skew. I was wondering if I can leave everything the way it is right now without affecting the performance.

Note: This design is a board that converts from PCIE to USB 3.0 using VIA-LABS VL805-Q6 Host Controller.

Additional Question:

  • did anyone understand where did the 20 picosecond in the first answer come from? how it was calculated?
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The propagation velocity on most flavours of FR-4 is about 160 picosecond per inch (surface) to 175 picosecond per inch (internal).

.06 inch (60 mil in American parlance) gives about 9. 6 picosecond of skew.

Note that the 8 nanoseconds of skew is interlane skew. Within a pair you need to keep the skew below 10% of the unit interval which for 5Gb/s requires skew of less than 20 picosecond which you meet.

Any skew will cause differential to common mode conversion which can cause EMC related issues, but it is completely design dependent.

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  • \$\begingroup\$ Can you please elaborate more how did you calculate the 20 picosecond? \$\endgroup\$
    – Xhero39
    Apr 27 at 13:14

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