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I'm trying to understand how Vg is calculated in this circuit below. I understand the current mirror is meant to protect the SMPS from current flowing into the output of J2 if the 12V source is not present by ensuring Q2 is open.

SMPS with current mirror controlled switch

I have modelled it in LTSpice below using a resistor for the load but the IR6 doesn't match the IR7. Even without the load the IR7 is still not equal to IR6.

How do I derive VG for a given load?

Note: Q1 in the schematic is a DMMT5401 which is a matched PNP pair in a single package. The LTSpice model uses 2 DMMT3906 to simulate the matched pair.

enter image description here

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  • \$\begingroup\$ This is a differential Common Base Amplifier with your Q2 Turning off and thus M1 turning on with Vg towards 0V if V1 > Vload. The ratio of R6/R3 is a fine adjustment for matching the Vbe voltages and effectively is a mV offset adjust. \$\endgroup\$ Commented Apr 28, 2021 at 4:08

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I have modelled it in LTSpice below using a resistor for the load but the IR6 doesn't match the IR7. Even without the load the IR7 is still not equal to IR6.

In an inverse current mirror, it's assumed that the transistors are matched and emitters are shorted:

schematic

simulate this circuit – Schematic created using CircuitLab

But, in the OP's circuit, it's almost impossible to match the collector currents because \$\mathrm{V_{BE-Q1} = V_{DS-M1} + V_{BE-Q2}}\$. And, as you might already know, \$\mathrm{V_{DS-M1}}\$ is proportional to load current: \$\mathrm{V_{DS-M1} = R_{DS}\cdot I_L}\$. I don't know if the MOSFET is fully modeled in the simulator, but from the datasheet, it can be seen that \$\mathrm{R_{DS-on}\approx25m\Omega}\$ for \$\mathrm{I_{LOAD}=1A}\$ and \$\mathrm{V_{GS}=-4.5V}\$. This means that the drop across the M1 will be around 25 mV. So the difference of \$\mathrm{V_{BE}}\$ between Q1 and Q2 will be 25mV, theoretically.

How do I derive VG for a given load?

Since the Q1-Q2 pair does not form a real inverse current mirror, \$\mathrm{I_{C-Q2}}\$ will not be completely dependent on the R6 (or in other words, Q1's collector current). Instead, it'll be more dependent on \$\mathrm{V_{BE-Q2}}\$ and the load current.

schematic

simulate this circuit

I couldn't really derive Vg but I can say that the idea is to keep Q2 off when VS is positive and greater than VO, and the load current is non-zero. Q2's crucial role is to force M1 off when the voltage is applied from VO-side instead of VS-side. So it may not be needed to be turned on during the normal operation.

When M1 is on, since the load current flows through RDS of M1, there'll be a drop across M1. The higher the load current, the higher the drop across M1, and finally the more the Q2 reaches turn-off (because VBE approaches more to zero). The lower the load current, the more likely the VBE of Q2 to be equal to that of Q1. This leads the Q2 to turn on more and make R2's upper-end voltage nearly VO. So M1 will turn off because its VGS becomes zero.

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  • \$\begingroup\$ Thanks Rohat, I see what you mean that it's not a traditional current mirror due to the FET. How best to drive Vg from VBE-Q2? \$\endgroup\$ Commented Apr 28, 2021 at 17:28
  • \$\begingroup\$ @DarrenBeckwith Sorry, I couldn't derive an equation for Vg. See the updated answer anyways. May this be helpful. \$\endgroup\$ Commented Apr 28, 2021 at 20:44
  • \$\begingroup\$ Rohat, thanks for the explanation it brings some clarity. I'd still like to understand how to drive Vg (I've been trying it all day on paper) but still haven't solved it. \$\endgroup\$ Commented Apr 29, 2021 at 4:31

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