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I am designing fast digital lines for the first time. I want to change the PCIe connector of the CM4 IO board to mini PCIe.

I reviewed the AN307: Hardware Design Considerations for PCI ExpressTM and SGMII. Pages 35 - 44 give the design and layout considerations.

  1. What does the "via sites" in "Stitching vias (to GND) at all diff pair via sites" mean?
  2. "Vertical and horizontal routing increases dielectric loss" - by "vertical and horizontal" do they mean "traces that go upwards/downwards and left/right?
  3. There is no reference to PCB stackup. Doesn't it matter?
  4. Are there other considerations I should take into account? (I'd appreciate a recommended app-note).
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