I am designing fast digital lines for the first time. I want to change the PCIe connector of the CM4 IO board to mini PCIe.
I reviewed the AN307: Hardware Design Considerations for PCI ExpressTM and SGMII. Pages 35 - 44 give the design and layout considerations.
- What does the "via sites" in "Stitching vias (to GND) at all diff pair via sites" mean?
- "Vertical and horizontal routing increases dielectric loss" - by "vertical and horizontal" do they mean "traces that go upwards/downwards and left/right?
- There is no reference to PCB stackup. Doesn't it matter?
- Are there other considerations I should take into account? (I'd appreciate a recommended app-note).