Are Verilog and VHDL Register Transfer Languages?

Question

I have seen the term Register Transfer Language being used as the expansion of RTL in the context of Hardware Description Languages (HDLs). Specifically over here: https://www.cl.cam.ac.uk/teaching/1011/SysOnChip/socdam-notes1011.pdf (Lecture notes on System On Chip Design and modelling by the University of Cambridge). Also see these slides by Princeton University : Lecture 15: Register Transfer Language and Verilog

At my university, I have been taught that RTL is a design abstraction which stands for Register Transfer Level and is used to denote a level for describing digital systems at the behavioral level as transfers between registers.

I have also heard about Register Transfer Language as an Intermediate Representation (IR) used by compilers such as GCC.

See https://llvm.org/pubs/2010-06-06-Clang-LLVM.pdf

The RTL is an assembler language for an imaginary processor architecture. It is passed on to the backend, which converts it into the machine code for the target architecture.

From a technical point of view, is the use of the term Register Transfer Language for HDLs correct?

Answer 1

Before the advent of compilers and synthesis tools, a Register Transfer Language (RTL) was any notation used by processor and micro-architects that described the timing and transfer of data between inputs, registers, or memory. These descriptions were used as instructions to hardwire the first computers with jumper cables or switches.

This terminology was taken up by tools in the process of taking RTL source text and synthesizing it into either machine code for software compilers, or circuits for hardware.

At some point during the introduction of RTL synthesis tools, people wanted to distinguish between transistor-level, switch-level, gate-level, and RTL-level abstraction of descriptions, and they started switching the L word Language to Level (and sometimes even Logic).

Over the decades, RTL has come to mean any portion of a hardware description that is fed into a synthesis tool, regardless of any registers or gates in the source code. So you really have to know the context where RTL is being used as input to a tool, or a level of coding abstraction. We are stuck with dealing with it.

Answer 2

RTL is a style of coding where clocked elements are expressly implied. This is generally done because synthesizers are not generally designed to design state machines on their own. While they often shine at logic optimization, they are not sophisticated enough to design all the synchronous timing from an abstract description.

HDLs such as VHDL and Verilog support RTL, but they aren't equivalent. Both languages also support behavioral descriptions, which are more abstract and allow efficient simulations of systems at more of a block diagram level to ensure the design is correct on a system level, and gate level descriptions, in which each individual element is instantiated explicitly. Gate level designs are often generated by synthesizers, but can be written directly.

Answer 3

While previous answer doesn't directly answer the question, it provides a common understanding of how RTL should be read regarding digital design topics, at least according to my engineering and teaching experience.

Opposed to that, from slides at the first two links in your question, I got an impression of sloppily mixed concepts and terminology (note, that this is just my impression regarding only the "RTL" term usage in the slides). Moreover, this is the first time ever that I see "RTL" as abbreviation of "Register Transfer Language" and not "Register Transfer Level" in the context of digital design. The third link, which describes Register Transfer Language in the context of a processor architecture, seems to use it correctly, though.

I've dug a little through the history of publications of the first link's author to see if the author uses "RTL" in the same manner now. Here are examples of using "RTL" in a more recent publication, c. 2019:

Although there is no accepted taxonomy of high versus lowlevel languages for hardware design, we can roughly relate a gatelevel netlist to machine code, RTL to assembly language, ...

Programs in a ‘Hardware Construction Language’, such as Chisel, essentially ‘print out’ an RTL or structural design ...

Further instances use "RTL" in same the manner, i.e. as an abstraction level of a design, except one phrase, which may imply "Register Transfer Language":

The generate statements of Verilog and VHDL form the hardware construction languages of those RTLs.

Thus, despite not expanding "RTL", the author consistently uses it in a sense of "Register Transfer Level" and not "Register Transfer Language". This confirms my initial impression of terminology mixup in the slides.

So answering your question, I would say that the use of the term Register Transfer Language for HDLs is incorrect.

Answer 4

1. In the abstract of the IEEE Std 1800-2017 it is stated:

Abstract: The definition of the language syntax and semantics for SystemVerilog, which is a unified hardware design, specification, and verification language, is provided. This standard includes support for modeling hardware at the behavioral, register transfer level (RTL), and gate-level abstraction levels, and for writing testbenches using coverage, assertions, object-oriented programming, and constrained random verification. The standard also provides application programming interfaces (APIs) to foreign programming languages.

From this it is clear that RTL is an abbreviation for Register Transfer Level in the context of SystemVerilog.

2. In the Appendix of the Accellera SystemC Synthesis Subset Language Reference Manual:

A.4.4.2

Implementation RT Level

Register Transfer Level (RTL), as the name suggests, describes functions and signals from registers to registers. The basic elements of this level are combinational and sequential functional/logic units, registers, and signals.

3. I am not able to access the VHDL Manual so trusting this resource:

The VHDL language standards committee offers this definition for RTL: “The register transfer level of modeling circuits in VHDL for use with register transfer level synthesis. Register transfer level is a level of description of a digital design in which the clocked behavior of the design is expressly described in terms of data transfers between storage elements in sequential logic, which may be implied, and combinatorial logic, which may represent any computing or arithmetic-logic-unit logic. RTL modeling allows design hierarchy that represents a structural description of other RTL models.”

Source: https://doi.org/10.1016/B978-075067866-7/50008-1

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This resource I found also sheds light on this issue:

1. To software developers, RTL may mean register transfer language. An example is the generation of an intermediate file format produced by a compiler such as gcc, during the translation of C code to machine language for a specific microprocessor.
2. To microprocessor designers, RTL may be conceived as a pseudo-code description of an instruction set architecture, describing the dataflow between different elements of the processor.
3. To FPGA designers, RTL stands for register transfer level, a relatively low level of abstraction allowing the description of a specific digital circuit. RTL can also be used to mean a hardware description language (VHDL, Verilog, SystemC), where “RTL” code is a lower level of abstraction than “Behavioral Level” code, although both are actually subsets of the full scope of HDL languages.

Source: https://www.sciencedirect.com/topics/computer-science/register-transfer-level