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In theory at least, SOIC is half the pin pitch of DIP and SSOP is half again. Thus SSOP is 0.1/4 = 0.025" or 0.635mm. Except I see many parts, from TI and Linear especially, which are SSOP (or TSSOP) with 0.65mm pin pitches. Which is slightly annoying.

Unfortunately, after say 18 pins in a row, the difference starts to add up so one has to be careful when adding footprints in Eagle.

The question is: was there ever really a standard for these parts or are manufacturers free really to do what they want? Or is this a metric vs imperial thing. There are 0.5mm TSSOP parts of course but they are more obvious.

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  • \$\begingroup\$ I understand if this gets closed - it's not so much a tech question as a matter of curiosity. \$\endgroup\$ – carveone Jan 28 '13 at 12:24
  • \$\begingroup\$ I just noticed this too - very annoying! I thought 0.65 mm was the "standard" until I found TI parts use 0.635 mm. \$\endgroup\$ – Timmmm May 7 '15 at 12:55
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It's not because 0.635 and 0.65 are close to each other that they're meant to be the same. There are also 2.5 mm pitch connectors next to the more standard 0.1" = 2.54 mm. Metric vs imperial. They're just different things which should be treated as such.

Note that with packages going further away from DIP the imperial standard is often abandoned in favor of metric. For instance DFN and QFN are mostly 0.5 mm pitch, and other dimensions are in mm as well, like in this drawing. Dimensions for SMD in inches becomes rare.

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  • \$\begingroup\$ Actually I'd forgotten that about the 2.5mm pitch connectors, especially as everyone uses the 0.1" pin headers (they're cheap, common and farnell charges way too much for 2mm). That's pretty much the answer. I was wondering did 0.025" get metricised into 0.65 but, as you say, they're different. \$\endgroup\$ – carveone Jan 28 '13 at 12:56
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    \$\begingroup\$ @carveone: yeah, I also think 2.5 mm is just to switch to metric, because the 0.04 mm you save per pin won't make that much difference. \$\endgroup\$ – Federico Russo Feb 2 '13 at 18:08
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There isn't really anyone holding them accountable or is going to throw them in jail if they go off spec. The way in which package drawings get standardized is more of a consensus building process rather than a top down enforcement of standards.

SSOP being 1/2 of SOIC isn't something set in stone. In fact, until you mentioned it, I never really saw it as such. I'm actually used to 0.65mm and would grumble at 0.635 if I ever saw it.

Each manufacturer gets to pick whatever size they feel like using. While in the long run it becomes economically advantageous to be with the consensus size as opposed to against it, until these standards are actually established enough to be ubiquitous each manufacturer is free to pick their own horse. It takes time for the consensus to evolve, mostly because the high inertia involved with changing manufacturing process makes it economically unviable to change sizes as soon as you start to realize your horse is not going to win the race.

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  • \$\begingroup\$ Very true. As an engineer I guess I wish for more consensus though, especially as I started with 0.1" through hole - you can place parts with a pen and gridded paper, and I did. I'm grumbling a bit at the extra work SMD makes me do! \$\endgroup\$ – carveone Jan 28 '13 at 13:01

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