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For my master thesis, I am designing a wireless power transfer using magnetic resonance. For this purpose, I designed a full bridge inverter which is connected to an autotransformer whose output is rectified (this way I can gradually increase my DC input voltage).

The bridge is driven by two IR2110 drivers which are connected to a dspic30F1010 microcontroller. The microcontroller generates four PWM signals of constant 50% duty cycle. (edit: with a dead time of 50 ns, so not exactly 50% duty cycle).

The system works fine and I was able to transmit about 700 W during 30 minutes without any problems. Yet, when I increase my input voltage to a certain value (a bit less than 300 V), one leg of my bridge fails.

The right leg of the bridge works fine and keeps a nice 50% duty cycle, but the other leg shows the following features:

Vds of the TOP MOSFET of the failing leg

Figure 1: Vds of the TOP MOSFET of the failing leg


Vds of the BOTTOM MOSFET of the failing leg

Figure 2: Vds of the BOTTOM MOSFET of the failing leg

The first picture shows Vds of the top MOSFET and the second one shows Vds of the bottom MOSFET. One can see that the top MOSFET gets turned off every 4 PWM cycles.

On the second picture, one can see that the current keeps flowing via the bottom MOSFET when the top one fails (I think it flows through the body diode, because Vgs remains low during that moment).

The following picture shows a picture of Vgs of the failing MOSFET (the top one):

Vgs of the failing MOSFET (TOP MOSFET of the failing leg)

Figure 3: Vgs of the failing MOSFET (TOP MOSFET of the failing leg)

First, one can see that it is really spiky and not stable. I'm not sure whether this kind of behaviour is normal with a bootstrap system or not. Then, one can see that during the glitch, Vgs almost remains zero all the time.

It also seems that the measurement itself impacts the phenomenon, as it happens every 4 cycles when measuring Vds and is much less regular when measuring Vgs (it seems to be every 5 cycles on the picture, but it is not always the case though).

I also checked the control signals coming from my microcontroller. These stay 4 nice PWM signals as expected.

The following pictures may help you to better understand my layout. The first one shows the PCB itself, in case it might be linked to the layout:

PCB of the inverter

Figure 4: PCB of the inverter

Then the following two are diagrams of the circuit and the components that I used for the design.

The 100 ohm - 100 pF is used to filter out high frequency glitches at the output of the microcontroller and the 4.7 kohm resistor is a pull-down resistor to avoid short-circuiting the bridge at start-up.

The MOSFETs are STW28N60M2, the gate diode is V2P6X and the bootstrap diode is GB01SLT06.

[edit: I changed the following picture to remove the ambiguity on the capacitor value]

Microcontroller circuit

Figure 5: Microcontroller circuit


H-bridge & drivers circuit

Figure 6: H-bridge & drivers circuit

This behaviour is something I never met before and I really can't find any explanation. It is even more strange to me because it occurs only in one leg and only after a given voltage value.

I tried changing the bootstrap capacitor value (lower & higher), I tried changing the gate resistor value, I tried to replace the IR2110 and the MOSFETs, nothing solved the problem.

Did anyone ever meet a similar kind of behavior, or does anyone have a clue on how to solve this?

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    \$\begingroup\$ You mention in a comment on Andy's answer that you have 50nSec dead-time between the phases, but it looks to me as though the RC time-delay due to the 100R/100nF filter on each of the control signals between the dsPIC and IR2110 drivers is an order of magnitude larger than that. Tolerances on those components probably overwhelm that relatively tiny 50nSec dead-time, resulting in shoot-through on certain channels. \$\endgroup\$
    – brhans
    May 3 at 14:19
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    \$\begingroup\$ There should not be any "high frequency glitches at the output of the microcontroller" to filter out anyway - I think your attempt to fix a problem that's not really there has caused you more trouble... \$\endgroup\$
    – brhans
    May 3 at 14:22
  • \$\begingroup\$ Thanks for the answer. I will try to remove these filters and see what it gives. \$\endgroup\$ May 3 at 14:23
  • \$\begingroup\$ But the shoot-through would cause a failure of the bridge (by shrot-circuit Vbridge and gnd) rather than just this kind of glitch, no ? \$\endgroup\$ May 3 at 14:24
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Your deadtime and Vgs are not shown which must be done with proper > 100MHz probing techniques to eliminate probe ground inductance of ~1nH/mm into the probe cable capacitance using a spring coil on tip/ring or FET diff probes. For this reason , your xx ns risetime test points ought to be twin vias for the sig.+gnd. to match the gap of the spring probe. Improvise for now.

Possible causes of failure are;

  • excessive Vgs from parasitic mutual inductance in ESL with positive feedback from source to Vgs max. exceeding breakdown voltage on high left side FET with PWM on low side Drain from parasitic mutual coupling of V= ESL*dI/dt
  • Excess heat rise from turning off same FET while Vds rises and inductive current continues (or lower than resonant load coil/cap frequency from reducing capacitive loads (or tuning error at high voltage) or high Miller currents during switching (record Temp rise vs Power output vs Vin and try a 4kW or a 16kW WPT design now achieved for WPT.
  • the main deadtime control comes from the 26 ns nominal deadtime in the IR2110 and the difference in rise fall times from the diode RD * C diode (1000pF) time constant much lower than the 3R * Cdiode both in shunt with Ciss of the power FET.
    • thermal effects on lowering Vt or Vgs(th) and wide tolerances may not be significant if the risetime is <10ns, but verify.

FWIW there are thousands of published works on kW level WPT on Google Scholar and Microsoft Academic (over 21k articles, some which may be useful to cite)

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The microcontroller generates two PWM signals of constant 50% duty cycle.

The IR2110 does not incorporate anti-shoot-through circuitry and you have made no mention that your digital input signals are designed to provide a small period of dead-time that prevents both MOSFETs (top and bottom) being simultaneously activated for a short period of time. When this happens you get a massive pulse of current that can easily destroy MOSFETs and, symptomatically, this gets worse as you raise the supply voltage.

The other problem is this: -

enter image description here

I can't tell whether you mean either 0.1 μF (100 nF) or 0.1 mF (1,000 μF) but, either way, they are too big. Your text implies 100 pF and that has a CR time of 10 ns but that only gets you 63% of the charging voltage so, you could be eroding your dead-band quite significantly if indeed you are using 100 pF and not anything higher.

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  • \$\begingroup\$ Thanks for the fast reply !Yes, indeed. I forgot to mention it, but I have a dead time of 50ns \$\endgroup\$ May 3 at 14:13
  • \$\begingroup\$ Then you don't have 50% duty cycle (as per your question). 50 ns may not be enough when you have an inductive load - try running it in a simulation to see why @JeanLouisDavid \$\endgroup\$
    – Andy aka
    May 3 at 14:13
  • \$\begingroup\$ You got me there, but you understand the idea, right ? Ok, I will dig in that direction \$\endgroup\$ May 3 at 14:15
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    \$\begingroup\$ The schematic says 0.1 mF or 0.1 uF - it categorically DOES NOT say 0.1 nF \$\endgroup\$
    – Andy aka
    May 3 at 14:29
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    \$\begingroup\$ Probably better to change the real schematic to pF so there is no ambiguity. \$\endgroup\$
    – rdtsc
    May 3 at 14:36

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