# shift register confusion It is a typical picture of a shift register. Assuming initially the clock is off, and serial input=1. After a while clock turns on, and immediately Q_2 becomes D_2=1, but since the clock is common to all flip flops, Q_2=1 means D_1=1, and Since the clock is still on D_1 SHOULD BE EQUAL TO Q_1, so, D_2=Q_2=D_1=Q_1=1, Similarly in can be shown that just after one clock pulse the serial input=1=serial output, which is not how the shift register should work. What is missing here?

• What is missing here? - set up time for data prior to a clock edge and propagation delay. D type flip flops are edge driven and not level driven. May 3, 2021 at 14:47
• There is a small but finite delay from the clock edge until the Q output actually changes. May 3, 2021 at 14:54

After a while clock turns on, and immediately Q2 becomes D2 = 1, but since the clock is common to all flip flops, Q2 = 1 means D1 = 1, and since the clock is still on D1 SHOULD BE EQUAL TO Q1, so, D2 = Q2 = D1=Q1 = 1.

Flip-flops are edge-triggered.

The outputs do not change immediately. There is a propagation delay.

Timing diagram.

         ________________________________________________
D2    __|
_______              ________
Clock ________|       |____________|        |____________
_________________________________________
Q2    _________|
____________________
Q1    ______________________________|


Note the delay between the clock and the Qs turning on.

Edge triggered latches and flip-flops have set-up times. This is the minimum time a value must be present on an input prior to the edge trigger in order for the device to "register" that input. If the clock edges arrive at each flip-flop simultaneously, even if the flip-flop had no propagation delay, a new value appearing at the output of a flip-flop will arrive at the input of the next flip-flop too late to meet the minimum set-up time, and so the 2nd flip-flop will not be toggled by that value. The minimum set-up time, and also the propagation delay prevent a change one flip-flop from rippling all the way down a shift register. (Image from ResearchGate)

In the image, $$\t_{su}\$$ is the setup time, and $$\d_{cq}\$$ is the propagation delay.