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I am currently designing a pretty big 4-layer development board 350mm x 270mm. Keeping in mind I have multiple analog digital and AC mains voltage, what would the best practice be regarding routing my 12V + 5V + 3.3V rails?

My options:

  • Option 1

    Route power rails on separate plane and stitch together the required polygon pours.

  • Option 2

    Use each plane for GND, 12V, 5V, 3V3 and stitch as needed.

  • Option 3

    Route power rails separately on multiple planes as needed.

With option 1 I will only use 1 plane (bot) for all my power rails, but have the analog and digital signals in-between. Could that cause EMI?

With option 2 I will have huge capacitance between planes?

With option 3 I have long fat traces running around my board.

What would the best option be (or the one with the least problems)?

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In a 4 layers board, at least 1 unbroken** plane should be for GND. Actually, for most 4 layers projects, I actually use 2 unbroken planes for GND.

About Power planes, ask yourself the following questions:

  1. are there power hungry high speed chips such as processors, FPGAs? If so, their supplies should each be tightly coupled to a GND plane, to create very low inductance planar capacitors. As a rule of thumb: when the necessary power supply impedance is below 1 Ohm at GHz, planar capacitance is in order. The necessary area depends on the required power supply impedance. For small RF chips a local power pour can be enough, whereas large processors might need a supply impedance of less than 10 mOhm and might require multiple power planes for the same rail. Violating this will affect both signal integrity and EMC. Also putting a power plane that is not tightly coupled to a GND plane, does not satisfy this bullet.

  2. for other power rails with no/negligible demand at 100MHz+ frequencies, it is often OK to route them (in a tree fashion to reduce common impedance coupling between consumers) and offer local decoupling caps. But still do pay attention to return currents in the GND plane. If you don't, EMC can be affected. Vias are also fine.

  3. for low frequency stuff, it is basically always ok to route power. But for precision analog, consider that PSRR is finite. So for precision analog even a 10mV droop on a 10V supply rail might affect signal quality, so choose your traces wide enough. Again it comes down to the desired power supply impedance. The return paths are less critical for these rails, but should be of a similarly low impedance than the supply traces, e.g. the GND plane. Another thing about precision parts: Even though you don't really reduce the power supply impedance in the e.g. audio band by adding a 100nF cap next to your opamps, I would still practise this. It makes the local supply voltage more immune to high frequency interference from nearby circuitry.

After going through 1-3 and you find that you need too much space for Power pours/areas/traces, you might find that you need to go to 6 layers. Cramming it in 4 layers while partially violating bullet (1) is not recommended if you care about signal integrity and EMC.

Your side question about EMI is a little related. If you need to route high speed signals, for the sake of signal integrity and EMI, pay attention to tightly coupled them either to a GND plane or their originating power plane for high frequency return currents. Most of the time in 4 or 6 layer boards, this means route over a GND plane, because there is no tightly coupled layer next to power (all of this layer is occupied by GND). In such stackups, IMO signals should be therefore on the same layer as the power distribution.

** you mentioned mains voltage. The layout safety rules for mains voltage demand that your isolated mains circuitry is not surrounded by the GND planes. your mains section should be physically separate (following clearence+creepage) with no overlap to any of your low voltage planes.

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    \$\begingroup\$ First of all thanks for this detailed reply. The board is low frequency with the fastest signal being the SPI bus so i think high frequency does not apply to my design. Also my main ADC is 16-bit while my secondary is 12-bit. Top layer is always GND and around the ADCs and their signal routing bottom layer is also GND. Thanks for the PSRR terminology (there are things to study there). Decoupling caps are used on every ic. Regarding the mains voltage traces/pours with HV differential are at least 5mm apart and GND doesn't go close to those but i do have many 12V relays. \$\endgroup\$ – geocheats2 May 4 at 11:24
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    \$\begingroup\$ If the relays are rated for mains voltage handling, then by design they obey the clearance rules between their load and signalling pins. About the other parts, it sounds like you don't need power planes at all and can route everything. As your board is fairly large, It's probably not much congested. In this case I suggest using two GND layers - one in each layer doublet - and routing signals and power always in vicinity of GND. If you cross your signal or power from the top layer pair to the bottom layer pair, place a GND via nearby so the return current can cross between the layer pairs, too. \$\endgroup\$ – tobalt May 4 at 11:46
  • \$\begingroup\$ What counts as power hungry? I posted a similar question yesterday, and you pointed me to this thread as well. I'm trying to decide on wether I need a power plane, for a transimpedance amplifier die, with a 2GHz bandwidth which consumes ~80mW of a supply of 3.3V. Thanks for the info, it's all very useful and informative! \$\endgroup\$ – genericpurpleturtle May 5 at 15:55
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    \$\begingroup\$ @genericpurpleturtle power-hungry is indeed maybe not the right term. I'll edit my post later. Important is, what is the tolerable signal effect due to a power rail disturbance. Multiply this with the amp's PSRR to get the maximum supply excursion and necessary power supply impedance. If the necessary power supply impedance is well below 1 Ohm at GHz, then you definitely need plane capacitance. But you might not need the entire plane and a local power pour can be enough to give you the necessary supply impedance. \$\endgroup\$ – tobalt May 5 at 17:07

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