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In my project I need a level shifter for a 3.6MHz clock. The problem I have with my design is that in order to respect the requirement I have, my rise and fall time need to be <25.2ns

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I used the following design, I tested first with the 2N7002 but it didn't even have the time to reach the 5V. When I simulate this design I have the following results:

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Based on the simulation I should have a 18ns rise time and almost instant fall time, but when implemented in practice I get a 40ns rise time. Do you think there is another MOSFET transistor (SOT23 package) that would make me shave off few more nanoseconds or I should totally rebuild my design ?

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    \$\begingroup\$ Why are you using a bidirectional shifter for a unidirectional signal? \$\endgroup\$
    – Dave Tweed
    May 4, 2021 at 14:42
  • \$\begingroup\$ I used it because it was the only design I knew would work without introducing a voltage drop \$\endgroup\$ May 4, 2021 at 14:45
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    \$\begingroup\$ My first question is, do you even need a level shifter? What device produces the 3.3V clock and what is the 5V device it goes into? Have you checked that the 5V device is not already compatible with 3.3V input signal? \$\endgroup\$
    – Justme
    May 4, 2021 at 14:52
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    \$\begingroup\$ Risetime depends on R1+R2=2k and load <10 pF and gain depends on R2/R1 during transition. If necessary (?) change R1 to 100 ohms and R2 to 470 Ohms \$\endgroup\$ May 4, 2021 at 15:15
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    \$\begingroup\$ Cin of FET needs lower R1 ... which IC is the load? \$\endgroup\$ May 4, 2021 at 15:23

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The FET pass gate level shifter is slow and is not suitable for the signal speeds you need.

Use a CMOS buffer chip that can work with 3.3V signal on input and will provide a 5V signal on output.

Since you now mentioned what you need it for, you should especially look for smartcard interface ICs that may provide you with many other benefits in addition to simply converting IO interface voltages.

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  • \$\begingroup\$ Thank you for your answer, that's what I suspected. I already have a design based on buffers that I validated. If you want to know more my idea was to design a Smartcard interface entirely in discrete component, because there is a shortage on SC ICs and I'm scared that buffers might lack sooner or later. \$\endgroup\$ May 4, 2021 at 15:12

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