# How do I make an edge triggered T flip flop using integrated injection logic (I2L)?

I have been searching everywhere online on how to make this circuit. I found out I can make NAND gates using I2L and connect them together to make a T flip flop , but this is very impractical since I will end up using 48 transistors.

I found a circuit for a negative edge triggered T flip flop using Bistable multivibrators .

I connected the circuit in Multisim and tested it , and it gave me the correct output for a T flip flop.

I figured that in order to make it I2L I have to replace every resistor in the circuit with a pnp bjt transistor ( 2n3906) as a current source and it should work, but it ended up giving me a really weird output.

I also came across a different circuit from 1980 of a "Triggerable flip flop" using I2L , but it used multi-collector npn bjt transistors and I don't know to make these. (https://patents.google.com/patent/EP0032154A1/en)

Thank you

• For most purposes, a multi-collector transistor is equivalent to two (or more) transistors with their bases and emitters connected in parallel. The transistors need to be well-matched for best results. Commented May 5, 2021 at 0:21
• What’s the fascination with 50 yr old technology replaced the following year by TTL , see p3 ti.com/lit/ds/sdls119/… Commented May 5, 2021 at 0:36
• Its a project I need to finish, I really don't care about or like the technology , for some reason the professor decided to assign a project to me where I have to make a simple component using an obsolete technology. Commented May 5, 2021 at 0:52

You cannot connect the emitter of a PNP transistor to +5V and the base to ground. That will burn out the transistor. Instead, you must include a resistor, either between base and ground, or between the emitter and +5V. I have only seen the later today, when researching I2L logic. (Actually it seems pretty interesting).

Although I don't have a circuit for a edge-triggered D-Flip-Flop, I do have an I2L circuit for an SR-latch. That should give you implementation ideas.

simulate this circuit – Schematic created using CircuitLab

[That part of the circuit that includes the relays and everything "below" the relays is there only for testing purposes. It is not part of the I2L SR-latch.]

Notice that there is a resistor between Vcc and the PNP transistor emitters. Changing that resistor will change the current consumed by the SR-latch.

The output of the circuit is:

Hope this get's you on your way!

I was able to fix the circuit I posted above by simply changing the value of the capacitors from 1uf to 1nf

Though if I added any value of resistance ( to the VCC) , it completely destroys the output.