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I'm designing a 4 layer PCB. The two outer layers are going to be routing layers, the 2nd layer a ground layer, and the 3rd layer a split power plane layer.

I have a negative and positive power supply, split on layer 3. These two supplies power three different voltage regulators. Two of these 3, create different bias voltages (to reverse bias photodiodes), and one one is used to create a 3.3V rail for an IC RF amp. Does it make sense to make the 3.3V rail a split power plane on the third layer? It only powers one IC, and since I'm amplyfing analogue RF signals, it needs to be as low noise as possible. What about making split planes for the bias voltages?

I guess more generally, when does it make sense to have a plane, vs a trace for a net?

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    \$\begingroup\$ If a power plane consists of just a single point-to-point connection there's not much point. Might as well just make it a trace. What's really important is the GND/reference plane which you want every trace using it to run over top of. \$\endgroup\$ – DKNguyen May 4 at 21:40
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    \$\begingroup\$ This question has some things in common with another one from today. So the answer can be helpful: electronics.stackexchange.com/questions/563421/… \$\endgroup\$ – tobalt May 4 at 21:50
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    \$\begingroup\$ Whenever dealing with ground/power planes, always analyze where the return currents / loop currents go (physically.) If your 1 component inadvertently causes a loop right near a sensitive analog section, having that plane can be worse than running a lone track. Bypass caps smooth voltage, but at the expense of increasing current delta; you want to avoid both voltage noise and current noise. (Which is why bypass caps are always placed as close as possible to the device being bypassed.) \$\endgroup\$ – rdtsc May 4 at 22:15
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If the chip has a lot of power pins, then a power "island" under it, with decoupling caps, makes sense.

However if it has only one power pin, then it doesn't make sense.

You say "RF" so I assume the inductance of the path between the power pin to the nearest decoupling cap is going to matter. In this case, from the pin, one via down to layer3, then another via (or maybe the same via) to a cap, then vias from the other side of the cap to ground... all this will probably have more inductance than a small decoupling capacitor placed right next to the power (and ground!) pins on the same layer as the chip. If the cap is right against power and ground pins, loop area is minimum, which is good.

Especially since on your 4 layer board, decoupling caps on top layer have the ground plane just below, so the inductance of their ground vias is lower than the ground vias of decoupling caps on the other side of the board, which have to go through almost all the board to connect to the ground plane. If the chip has power and ground pins next to each other, that's the way.

Note you can also use a feedthrough cap as decoupling cap. For example NFM21PS106 from Murata. In this case it does triple duty: decoupling, prevents HF from the chip from getting into the supply, prevents noise from the supply from getting into the chip.

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You don't need power planes for each power domain, especially if you have a ground plane. But there are some things to watch out for:

  • Trace inductance: this can result in increased noise at the component. Bypass well, and make traces wide enough to reduce impedance.
  • Power-to-signal coupling: noise spikes on your power feed can couple. Separate them from sensitive signals.
  • Plane-crossings: signals on the bottom layer should keep the same reference, and not cross between domains. If they do, bypass them at the crossing points.

Try to arrange your power supplies so that they form a 'star-tie' pattern and have return currents that don't interfere with each other. That is, each power domain should form a loop that is separate from the others.

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