Power on state of D Type Flip Flop

Question

I'm looking at the following two d-type flip flops to create a toggle for the EN pin on another IC.

I was going to feed Q back into D with an inverter such that it is toggled when clocked ( would this need a delay to not violate the hold time on D?)

https://assets.nexperia.com/documents/data-sheet/74AHC_AHCT1G79.pdf https://assets.nexperia.com/documents/data-sheet/74LVC1G175.pdf

My question is what the default state is when these power on. There is no mention in the datasheets. The second has a reset line so presumably I could have an RC delay on that so that VCC is fully risen before the reset goes high - but I am not sure if this is necessary, and in any case the first does not have a reset line, so does it expect/require an initial clock pulse to put it in a known state.

On a side question, as these are edge triggered, will it matter if the clock stays high for a long (1-2s) duration?

If there is a better (cheap) option to do this that would also be great.

Answer 1

There isn’t a hold time problem if you add an inverter - in fact this helps hold time, but subtracts from setup time.

No flip-flop is guaranteed to power up in a known state. They all require a set or reset to initialize them. You’ll need to add this, or design your logic so that it doesn't care.

As you said, the ‘79 flip flop could be initialized to a known state by forcing the input and clocking it. This requires an additional gate to the D input, and coordinating that state-forcing with toggling the clock. Probably more complicated than you want.

The ‘175 flip-flop has an asynchronous reset, which works regardless of the clock. You could indeed do some kind of RC circuit to make a reset at power on for a cheap-and-cheerful solution.

Finally, static flip-flops like these have no maximum clock period / minimum frequency. Dynamic flip-flops exist, but not as small ICs like the ones you’re working with here.

Answer 2

I was going to feed Q back into D with an inverter such that it is toggled when clocked ( would this need a delay to not violate the hold time on D?)

It's quite unlikely. There won't be any hold violation if the sum of flop's propagation delay and the delay of the inverter is greater than the hold time of the flop.

the first does not have a reset line, so does it expect/require an initial clock pulse to put it in a known state.

Yea, the first clock edge will drive the output of the flop to a known state assuming that the 'D' input is not floating. Otherwise the state of the flop is indeterminate. If reset/clear input is there, it has to be used to drive the output state of any flop to a known state at the power-on.

On a side question, as these are edge triggered, will it matter if the clock stays high for a long (1-2s) duration?

The value at Q remains latched until the next clock edge. There is a min. pulse width requirement on clock to make sure that the flop captures the data on the rising edge, however 1-2s is 'too long' compared to that.