I'm looking at the following two d-type flip flops to create a toggle for the EN pin on another IC.
I was going to feed Q back into D with an inverter such that it is toggled when clocked ( would this need a delay to not violate the hold time on D?)
My question is what the default state is when these power on. There is no mention in the datasheets. The second has a reset line so presumably I could have an RC delay on that so that VCC is fully risen before the reset goes high - but I am not sure if this is necessary, and in any case the first does not have a reset line, so does it expect/require an initial clock pulse to put it in a known state.
On a side question, as these are edge triggered, will it matter if the clock stays high for a long (1-2s) duration?
If there is a better (cheap) option to do this that would also be great.