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Given the above combinational logic diagram, How to calculate the propagation delay?
AND->OR->AND-NOT
NOT->AND->NOT
I see the above two longest paths. So what I understand is just take the maximum of these
two.

But is it fixed what's the propagation delay for an AND GATE and other gates?
I am not sure about the numbers.

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    \$\begingroup\$ If these are discrete parts, the datasheet should give the delay. If these are on chip, the library you're using should say what the propagation delay is for each type of gate. \$\endgroup\$ May 6, 2021 at 1:55

1 Answer 1

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So what I understand is just take the maximum of these two

You have to choose the path with max. delay in here to calculate the propagation delay. This path is called the critical path. To know that, you have to figure out each timing path to \$ F \$ and add respective delays. Since the final AND and NOT gates are common to all timing paths to \$ F \$, you just have to consider how is the combined delay of the other AND and OR gates, compares with the other NOT gate (paths from \$B\$ to the final AND gate).

But is it fixed what's the propagation delay for an AND GATE and other gates
I am not sure about the numbers.

It's not at all necessary these values are fixed for each gate. Different gates can have different propagation delays. And these values depend on operating conditions like voltage, temperature; input slew, fanout etc. These 'numbers' and trade-offs will be defined in cell library or in the datasheet.

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