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I designed a 4-bit JK up/down counter.

I want the circuit to be reset to 0 when counting up when it reaches 9, and to be reset to 9 when counting down when it reaches 0.

Anyone know how ? I tried a lot.

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  • \$\begingroup\$ Something like this? \$\endgroup\$ – jonk May 7 at 7:29
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    \$\begingroup\$ We won't do your homework for you. Show us what you did when you "tried a lot". Explain exactly why your design didn't work. \$\endgroup\$ – Elliot Alderson May 7 at 23:22
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What did you try?

It is very easy to design a JK synchronous circuit. In fact just draw the table giving the state Qn of each JK representing a bit and its transition on each clock like the following:

enter image description here

and then fill the corresponding JK as follows:

  • A transition from 0 to 0 is either a reset or a maintain: J=0, K=x
  • A transition from 0 to 1 is either a set or a toggle: J=1, K=x
  • A transition from 1 to 0 is either a reset or a toggle: J=x, K=1
  • A transition from 1 to 1 is either a set or a maintain: J=x, K=0

Where x is a don't care.

At the end, having the truth table of each Jn and Kn depending on all Qn you can simplify the expression and get the circuit of each Jn and Kn using logical gates.

In your case, include the U/D (up or down) input in the logic.

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