I'm learning about sequential logic and am wondering about the behavior of a clocked SR flip-flop.
If R=S=0, then the AND gates evaluate to 0. In that case, and if the recurrent inputs to the NOR gates are initially 0, then both evaluate to 1. But then the recurrent inputs will switch the output of the NOR gates to 0, which will then cause the NOR gates to output 1 again, and so on. Given the speed of electricity, wouldn't you end up with many oscillations of the output of this circuit within the space of a half clock tick? If what I'm think makes sense, does that mean that such a case must be avoided by initializing the circuit?