6
\$\begingroup\$

I'm learning about sequential logic and am wondering about the behavior of a clocked SR flip-flop.

http://en.wikipedia.org/wiki/File:SR_%28Clocked%29_Flip-flop_Diagram.svg

If R=S=0, then the AND gates evaluate to 0. In that case, and if the recurrent inputs to the NOR gates are initially 0, then both evaluate to 1. But then the recurrent inputs will switch the output of the NOR gates to 0, which will then cause the NOR gates to output 1 again, and so on. Given the speed of electricity, wouldn't you end up with many oscillations of the output of this circuit within the space of a half clock tick? If what I'm think makes sense, does that mean that such a case must be avoided by initializing the circuit?

\$\endgroup\$

2 Answers 2

Reset to default
5
\$\begingroup\$

First, personally I would refer to the circuit you show as a set-reset flip-flop with enable, also called a latch. I reserve the words register and clock for an edge-activated two stage memory element.

The instable situation you sketch does exist and is called metastablility. It occurs when both of the set-rest flip-flop inputs were 1, and both switched to 0 at the same time. This causes a time period in which the outputs can show weird behavior, like oscillation or values half-way between 0 and 1. Eventually the flip-flop will settle to a stable situation, with one output 1 and the other 0. This metastable period is short, but IIRC its length follows some statistical distribution, so it has a non-zero (but very very small) chance of extending to any given length.

Current-day chips are generally synchronous internally, which avoid the metastable problem. It can still occur at the edges (external inputs), where it is usually eliminated (to a very high probability) with two flip-flop stages in series, where the second one is enabled only after the metastable period of the first is (very probably) over.

\$\endgroup\$
2
  • \$\begingroup\$ Ok, so in a well engineered system S and R should never both be 1 anyways, because the behavior for that input is undefined, correct? What if the first input in the sequence is (0,0), could that also lead to metastability? If not, what would happen in that case? \$\endgroup\$
    – Matt Munson
    Jan 29, 2013 at 7:40
  • \$\begingroup\$ Correct, but when external signals (not synchronysed to an internal clock) are present this (or equivalent) situations can nt always be avoided. A second cause of metastability could be powerup. One way to prevent this is to include a hardware power-up reset. \$\endgroup\$
    – Wouter van Ooijen
    Jan 29, 2013 at 14:26
2
\$\begingroup\$

Scenario 1:

Let's assume the outputs from BOTH And gates are zero. And also assume /Q =0. The top Nor gate will then have inputs of (0,0) -> NOR(0,0) = 1 = Q. With the Q output being 1 the lower NOR gate has inputs of (1,0) -> NOR(1,0) = 0 = /Q which we defined before.

Scenario 0: [ ;) ]

Let's still assume the outputs from BOTH And gates are zero. And also assume /Q =1. The top Nor gate will then have inputs of (0,1) -> NOR(0,1) = 0 = Q. With the Q output being 0 the lower NOR gate has inputs of (0,0) -> NOR(0,0) = 1 = /Q which we defined before.

So no oscillation, and the value is held, the situation that you describe, called metastability, cannot exist as you describe it unless you deliberately enforce it by asserting both A & B inputs. One of the NOR gates will win out, simply because of statistical variation. Upon power up, the same case exists, it basically comes up in an unknown state. One of those NOR gates will be just a little bit faster than the other.

To summarize, what you describe can only happen in a very abstract and ideal case.

\$\endgroup\$
4
  • \$\begingroup\$ I see what you're saying. But, before Q can make it to the bottom NOR gate, Won't the bottom NOR gate already have made an output, (0,0)->1, that is going to change the output of the top NOR? \$\endgroup\$
    – Matt Munson
    Jan 29, 2013 at 5:03
  • \$\begingroup\$ This is what is called a cross coupled latch. The holding state is with both AND gates outputs low. That means that to S (et) or R(eset) the latch one of those and gates will drive high. In that asserted state the latch takes on the value such that upon de-assertion the latch keeps that state. There is no rippling out or propagation upon de-assertion. Asserting BOTH S &R is an entirely different thing ... \$\endgroup\$
    – placeholder
    Jan 29, 2013 at 5:55
  • \$\begingroup\$ I'm not sure what you're saying. I know how the circuit is supposed to behave. Also, the behavior for set and reset makes sense to me. I'm just wondering about the specific caveat, regarding the mechanics of the circuit, that I have outlined. \$\endgroup\$
    – Matt Munson
    Jan 29, 2013 at 6:06
  • \$\begingroup\$ The case you're discussing exists either when both S & R inputs are high or in some ideal sense upon circuit start up. It is called metastability. In the start up case it basically cannot exist because there is no way for the circuit to be powered up without one of the NOR gates taking over. In this instance metastability manifests itself as either Q or /Q winning out once powered up. However which one wins out is not known, that is why circuits are typically reset to a known state before operation because upon power up their state cannot be certain. \$\endgroup\$
    – placeholder
    Jan 29, 2013 at 10:39

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service and acknowledge that you have read and understand our privacy policy and code of conduct.

Not the answer you're looking for? Browse other questions tagged or ask your own question.