DDS - find optimal size for LUT, PHACC and sampling freq for application

About the topic of DDS you can find a bunch of information on the net and i think i understood the basics relatively well.

You use a lookup-table with stored values of the function you want to put out. Then you increment the value of an accumulator periodically and put the value from the lookup table which index is according to actual value of accumulator to your DAC.

What i'm missing a bit in most of literature i read about this topic is how i find the most suitable size of Lookup table and phase accumulator for my application. Also i'm not sure how to find out most suitable sampling frequency or more precise the right amount of oversampling.

If you look at basic formula: f(out) = [tuning_word * f(sampling)] / size_of_accumulator You can determine that tuning word is the variable size you use to set up your desired output frequency. If you would increase sampling frequency you could use smaller tuning words but i don't think it would make sense.

The higher the sampling frequency is over the sampling theorem (2*signal_freq) the better the quality of my output signal gets, so sampling frequency should be as high as possible ?

The higher my accumulator is, the more increments can be done before it is filled which means accuracy get's increased so choose accumultor as big as possible also ?

Or is it more the size of lookup table defining the accuracy or both of it, so make both, the lookup table and the phase accumulator as big as possible and choose tuning word accordingly to reach prevailed number of increments ?

Or what is the criteria you are using to determine these parameters implementing your DDS ?

Greetings

• It all depends on the kind of waveforms you want to generate, and how "good" they need to be (amplitude and phase error). Generating sines/cosines can be done with relatively small tables (only need one quadrant of values), and can also make use of interpolation techniques to reduce the LUT size significantly. Arbitrary waveforms are a different story. May 8, 2021 at 13:17
• Ok thx for reply, and is this also similar for finding the most suitable method of implementation (Discrete Synthesizer Chip, Microcontroller, FPGA, PLL+NCO) ? May 13, 2021 at 14:59

how i find the most suitable size of Lookup table and phase accumulator for my application?

First of all, you define the requirements of your application.

There are many factors that might be important, including

resolution frequency
maximum frequency (absolute, or as a fraction of the clock)
phase noise
amplitude noise
spurious performance

Generally, a DDS with a lot of accumulator bits will give you good frequency resolution, and a lot of DAC bits will give you good noise and spurious. But how 'good' do you need them?

I had a DDS application where no close-in spurious was permitted, (well, OK, it wasn't none, but it was over 60dB better than a simple DDS, which would have been unachievable with obtainable DACs). Fortunately I could sacrifice resolution, and was working in an FPGA, so could vary the accumulator size depending on the output frequency, so that I was always generating a small rational fraction of the clock frequency. Now I had aliased harmonics in predictable places, rather than unpredictable spurs.

If you know exactly what performance you need, then this will drive the design of your DDS, as it did mine above. If you don't know exactly what you need, set a budget, and with your required maximum and resolution frequencies, choose the most DAC bits your budget will cover. The accumulator will invariably be long enough so that phase noise is dominated by the DAC rather than accumulator. Then use it for a bit, and discover whether it meets all the requirements you didn't realise you actually had.

• Ok thx for reply, and is this also similar for finding the most suitable method of implementation (Discrete Synthesizer Chip, Microcontroller, FPGA, PLL+NCO) ? May 13, 2021 at 15:01