Any CPU has address pins which form it's physical address space. Some peripherals, like ram or flash can be classified as one big data register which is mapped directly to CPU address space. On the other hand, same peripherals can be connected to system via bus device, and becomes accesible using bus registers by special protocol(e.g SDC/MMC flash via SPI).

Am I right, that in the second case, spi becomes level 2 bus also becoming a peripheral itself(from CPU's point of view)?

What are proc and cons of first and second way of connecting peripherals?

Is it possible to map e.g SPI flash memory to address space, to avoid manual interaction with SPI bus every time? As I know, PCI bus allows to do something like that.

  • \$\begingroup\$ Can you define what you mean by a "level 2 bus"? Also, what do you mean by "manual interaction with SPI"? The word "manual" implies that something is done "by hand", but there are no hands involved here. \$\endgroup\$ May 8, 2021 at 20:48
  • \$\begingroup\$ Some higher end MCUs have various peripherals that for example allow direct mapping of memory chip that is connected behind SPI bus to main memory space for code execution, so yes, it is possible. \$\endgroup\$
    – Justme
    May 8, 2021 at 20:50
  • \$\begingroup\$ @ElliotAlderson Alderson By level 2 bus, I mean bus connected to initial system bus. By "manual" I mean making PSI transaction in application code. \$\endgroup\$
    – ser
    May 8, 2021 at 20:54

1 Answer 1


SPI doesn’t have a notion of address by itself. Memories that are attached to SPI (NOR flash especially) can be mapped to system memory addresses using a layer on top of SPI to translate IO accesses to SPI accesses. One mechanism to do that is execute-in-place, or XIP, which is supported by some microcontrollers.

Hyperbus is an evolution of SPI, and supports more general memory I/O, with PSRAM and DRAM as well as flash devices available for it. It, too, would use a translation layer for memory-mapped access.

If the system supports virtual memory, a more general mechanism can be used to manage memory attached to SPI or other slower external buses. When a page fault occurs, the kernel loads or unload pages from or to the slower device as needed. This would be more efficient than stalling the whole system while a memory request is satisfied by SPI. Further, it doesn't need a memory-mapped hardware translation layer, and can allow other processes to move along while the faulting process waits for its pages.


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