That division operation works fine fine. It just treats everything as a truncated integer. However, be aware The clock is not a regular signal that runs through the logic fabric. Clock signals on FPGAs are distributed through one of the clock distribution networks on the FPGA in order to minimizes skew. There are only a limited number of these networks on the FPGA. This is why you use the hardware PLL or divider on the FPGA. The "posedge" keyword tells the software that the signal used with it should be routed through the clock distribution network and not treated as a regular signal.
Running a clock through logic is bad practice and unreliable. Are you sure you don't need a clock enable instead that triggers every n clock cycles?
You only truly need a slower clock if you have a logic sequence so long that it cannot finish within a shorter clock cycle, and if this is the case you should use the hardware clock divider and distribution. Otherwise, you can just run a fast clock and just execute every n clock cycles.
A clock enable is a pulse that lasts for only a single clock cycle and is used to trigger other blocks to run. This allows the other blocks to be clocked off the hardware clock but not run every single clock cycle. Very important since many processes muck up the data flow if they are running every clock cycle but the system is not ready to feed them new inputs or receive their outputs.
A clock enable is very similar to what you have right now except that once the pulse goes high, you being it low again the very next clock cycle.
If that is what your assignment wants, fine. But if you actually try to divide a clock like that in a project and use it to clock things, it is going to bite you in the ass.