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I think I didn't explain myself correctly. Let me tell you in more detail.

I have 64 blocks: A, B, C, D ..... Each of these blocks is a parallel in parallel out shift register of n bits. The task of these blocks is to shift their contents from A to B, B to C, C to D..etc.

I'm having trouble sending the std_logic_vector type of data from one block to the other.

My code is given below. I've put comments on the lines that have the error.

library ieee;
use ieee.std_logic_1164.all;

entity Shift is

generic (
  Block_Size         : integer := 64;    
  Entry_length       : integer := 32     
);


port(
  new_entry:      in std_logic_vector(Entry_length-1 downto 0);         
  clk:            in std_logic;          
  reset:          in std_logic;          
  done:           out std_logic                             
 );

end Shift;

architecture Synchronous of Shift is
component ShiftReg
      generic (
           Entry_length  : integer := 32   
          );

      port(
          clk:            in std_logic; 
          reset:          in std_logic; 
          enable:         in std_logic;                                   
          data_in:        in std_logic_vector(Entry_length-1 downto 0);   
          data_out:       out std_logic_vector(Entry_length-1 downto 0)   
          );

end component;  

signal data_Shift_i : std_logic_vector(Entry_length-1 downto 0);
signal enable : std_logic; 

begin  
  Reg_i: for i in 0 to Block_Size-1 generate 
            i_Reg: ShiftReg
            generic map ( Entry_length => Entry_length
                ) 
            port map (  
                clk              => clk,
                reset            => reset,
                enable           => enable,
                data_in          => data_Shift_i(i-1),  -- error: cannot put (i-1)
                data_out         => data_Shift_i(i)     --error: cannot put (i)
              );
  end generate Reg_i;

end synchronous;
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You can put the components A and B in a new component (e.g. AB) and instantiate that new component n times with a generate.

gen: for i in 1 to 64 generate

   i_ab: entity work.ab
      port map(
          ....
          ); 

end generate gen;
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  • \$\begingroup\$ I think I didn't explain myself correctly. Let me tell you in more detail. \$\endgroup\$ – Orange Feb 3 '13 at 7:49
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There is a problem with the binding of your ports to the signal. The ports are 32 bits wide. Your signal at toplevel who is connecting e.g. A with B is also 32 bits, but you're using only one bit for the connection!

I would create a new type:

type t_interconnect is array (0 to Block_Size) of std_logic_vector(Entry_length-1 downto 0); -- the new type
signal interconnect of t_interconnect; -- the signal of the new type to be used 

You can assign the input of the topmodule to the first index of 'interconnect'. And further connect the 'data_in' and 'data_out' as in the example. The last index of the array is then the output of the last module in the chain and should be assigned to the output of the toplevel.

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  • \$\begingroup\$ Thank you Vermaete! That was really helpful. I have another question regarding this: If i want to initialize all the blocks with a value, ie data_in of each of them will get a Entry_lenngth bit unique value. I have another program which generates random numbers every clock cycle (So it needs to be inside a process). How can I loop through all the components at each clock cycle and initialise them with the values? \$\endgroup\$ – Orange Feb 6 '13 at 14:30
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data_Shift_i is only 32 bits wide. Your for loop goes from 0 to 63 so you are trying to access bits of data_Shift_i that don't exist. However, I think that is just the first of your problems.

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