I think I didn't explain myself correctly. Let me tell you in more detail.
I have 64 blocks: A, B, C, D ..... Each of these blocks is a parallel in parallel out shift register of n bits. The task of these blocks is to shift their contents from A to B, B to C, C to D..etc.
I'm having trouble sending the std_logic_vector type of data from one block to the other.
My code is given below. I've put comments on the lines that have the error.
library ieee; use ieee.std_logic_1164.all; entity Shift is generic ( Block_Size : integer := 64; Entry_length : integer := 32 ); port( new_entry: in std_logic_vector(Entry_length-1 downto 0); clk: in std_logic; reset: in std_logic; done: out std_logic ); end Shift; architecture Synchronous of Shift is component ShiftReg generic ( Entry_length : integer := 32 ); port( clk: in std_logic; reset: in std_logic; enable: in std_logic; data_in: in std_logic_vector(Entry_length-1 downto 0); data_out: out std_logic_vector(Entry_length-1 downto 0) ); end component; signal data_Shift_i : std_logic_vector(Entry_length-1 downto 0); signal enable : std_logic; begin Reg_i: for i in 0 to Block_Size-1 generate i_Reg: ShiftReg generic map ( Entry_length => Entry_length ) port map ( clk => clk, reset => reset, enable => enable, data_in => data_Shift_i(i-1), -- error: cannot put (i-1) data_out => data_Shift_i(i) --error: cannot put (i) ); end generate Reg_i; end synchronous;