# Calculating how long it takes for a circuit to compute the output for a given set of inputs

I'm having trouble with analyzing a circuit with respect to time, given clock-to-q, setup, and delays of individual components. We are given that

• $$\t_{clk-to-q} = 3ps\$$
• $$\t_{setup}=4\$$
• $$\t_{shifter}=1\$$
• $$\t_{adder}=5\$$
• $$\t_{multiplier}=6\$$
• $$\t_{subtractor}=4\$$.

We are also given that the inputs A, B, and C take on their new values exactly at the rising edge of every clock cycle and that all registers are intialized to zero.

This is the pipelined circuit:

(Sorry, some of the components I don't know how to represent in the circuit maker thing)

Anyway, the question asks:

How long does it take to compute the output for a given set of inputs? Assume the clock period is 11ps.

And the answer and explanation are given as:

Technically, 30ps is the time it will take for the values of one set of inputs to propogate to the output, We also accepted 41ps (3 clock cycles + clk-to-q + adder)

I'm confused on how they got that. Currently, I am calculating 31. Im taking the path from input B to register 2 to the output, which is (setup + adder + clock-to-q + multiplier+ adder + clock-to-q + adder) (I think)

What am I doing wrong?

DISCLAIMER: THIS IS NOT A HW QUESTION, I'M JUST STUDYING FOR FINALS AND DOING PRACTICE PROBLEMS

• Use \$ for inline MathJAX on EE.SE. (It's $ on other sites.) May 10, 2021 at 21:14
• @Transistor ty for letting me know, fixing now! EDIT - it doesnt seem to work :( I think it was displaying correctly before though May 10, 2021 at 21:20
• Have a look at the "edited x minutes ago" link to see how I fixed it. May 10, 2021 at 21:37
• None of the answers make any sense as there are setup violations at multiple paths in the circuit, for eg: Reg4 to Reg2. May 11, 2021 at 7:57