I'm having trouble with analyzing a circuit with respect to time, given clock-to-q, setup, and delays of individual components. We are given that

  • \$t_{clk-to-q} = 3ps\$
  • \$t_{setup}=4\$
  • \$t_{shifter}=1\$
  • \$t_{adder}=5\$
  • \$t_{multiplier}=6\$
  • \$t_{subtractor}=4\$.

We are also given that the inputs A, B, and C take on their new values exactly at the rising edge of every clock cycle and that all registers are intialized to zero.

This is the pipelined circuit:

enter image description here

(Sorry, some of the components I don't know how to represent in the circuit maker thing)

Anyway, the question asks:

How long does it take to compute the output for a given set of inputs? Assume the clock period is 11ps.

And the answer and explanation are given as:

Technically, 30ps is the time it will take for the values of one set of inputs to propogate to the output, We also accepted 41ps (3 clock cycles + clk-to-q + adder)

I'm confused on how they got that. Currently, I am calculating 31. Im taking the path from input B to register 2 to the output, which is (setup + adder + clock-to-q + multiplier+ adder + clock-to-q + adder) (I think)

What am I doing wrong?


  • \$\begingroup\$ Use \$ for inline MathJAX on EE.SE. (It's $ on other sites.) \$\endgroup\$
    – Transistor
    Commented May 10, 2021 at 21:14
  • \$\begingroup\$ @Transistor ty for letting me know, fixing now! EDIT - it doesnt seem to work :( I think it was displaying correctly before though \$\endgroup\$
    – Manny
    Commented May 10, 2021 at 21:20
  • \$\begingroup\$ Have a look at the "edited x minutes ago" link to see how I fixed it. \$\endgroup\$
    – Transistor
    Commented May 10, 2021 at 21:37
  • \$\begingroup\$ None of the answers make any sense as there are setup violations at multiple paths in the circuit, for eg: Reg4 to Reg2. \$\endgroup\$
    – Mitu Raj
    Commented May 11, 2021 at 7:57

1 Answer 1


You failed on two points:

  1. You did not recognize that the prof is playing games with your head.
  2. The delay from register 4 to register 2 contains an adder and a multiplier, which have an aggregate delay of 11ps, and the registers have clock-to-q and setup delays,.

Add these extra delays to the clock-to-q delay for register 4 and the setup delay for register 2, and -- when the temperature and clock frequency are just right and the process hasn't changed lately -- that'll add a reliable 'a bit more than 1 clock delay' to that signal path.

  • \$\begingroup\$ im confused, aren't we taking the full path from input B to Output? Or is it just from register 2 to 4? \$\endgroup\$
    – Manny
    Commented May 11, 2021 at 4:33
  • \$\begingroup\$ The question says "from the inputs to the outputs". So you have to look at all paths from all inputs to the output. \$\endgroup\$
    – TimWescott
    Commented May 14, 2021 at 16:16

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