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I generally tend to use vias close to the pin to connect my components to GND.

I was just wondering what is the right way to make connections when you have two components connecting to say 5V or GND. Should you connect them both on the same layer and use vias or one of the two?

For example, in the picture below (please ignore violation,) I have a component that needs to go to 5V. There is a 5V plane underneath all of this. Would you not connect them on the top layer and simply via it to the plane since that will be the shortest path, or would you have one connected to the plane and the other simply a net on the top layer - or does it not matter?

Example situation

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  • \$\begingroup\$ If you have a ground/power plane, then use vias to connect components to the planes \$\endgroup\$ May 11, 2021 at 9:55

3 Answers 3

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A via creates a routing block on all layers.1 This can come back to bite you later, when you're trying to complete the final connections, especially if your board is tightly packed.

A surface track also creates a routing block on one layer, and the outer layers are a particularly critical resource in SMT designs.

My normal approach is to start by placing the extra via, but then replace it with a surface trace if possible during the final cleanup passes toward the end of the editing process. Or sooner, if I get to a point where it becomes obvious that I won't be needing to route anything between the two components.


1 Blind vias block fewer layers, but add significant cost to the board.

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    \$\begingroup\$ What does HuA stand for; I've not heard the term before? \$\endgroup\$
    – Hearth
    May 11, 2021 at 12:37
  • \$\begingroup\$ @Hearth: That was a typo that my tablet inserted. Fixed. \$\endgroup\$
    – Dave Tweed
    May 11, 2021 at 14:42
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V transient depends on L dI/dt and L depends on path length and width ratio. But roughly if via is 1.5mm thick that adds 0.8nH/mm or 1.3 nH vs a trace which could a longer path length. So depending on dI/dt and ripple voltage specs and component ESR, you design your grounds and RLC equivalent circuit.

For microvias , the smaller the hole d/h ratio, the larger the L and so more microvias when using microwave signals reduce L and < 1/10 wavelength. This is identical to lower trace l/w ratios.

Obviously, this depends on BW susceptibility in all directions for conducted and reactive coupling and damping factor.

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  • \$\begingroup\$ nH/mm :) cant edit the typo because its too small. \$\endgroup\$
    – tobalt
    May 11, 2021 at 12:19
  • \$\begingroup\$ which typo?............ @tobalt \$\endgroup\$ May 11, 2021 at 12:27
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    \$\begingroup\$ you wrote 0.8 MILLIHENRY per mm. Also is it even 0.8 nH/mm ? This is for an isolated piece of wire, no ? If there is return conductors nearby, the effective inductance should be lower? \$\endgroup\$
    – tobalt
    May 11, 2021 at 12:28
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    \$\begingroup\$ Yes it is correct . Consult with Saturn PCB design if you want. THat ESL will vary +/50% over a wide range of H/D ratios or L/W on traces \$\endgroup\$ May 11, 2021 at 13:27
  • \$\begingroup\$ It was my obvious typo. Error. (Doh) There are many cases for analog, where this is negligible, but not for high speed logic and microwave. \$\endgroup\$ May 11, 2021 at 13:35
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Assuming this is some high speed chip.

The rule is: minimize the loop area encompassed by the IC's two supply and ground pins, the nearest storage capacitor, and the copper connecting the supply pins to this capacitor.

If you have power and ground planes, then these planes are the nearest capacitor. And you minimize the supply loop area by placing two vias near the supply pins. The via should be also near eachother.

If you don't have a supply plane, then manually add a capacitor in close proximity to the supply pins and route atightly packed connection pair between the supply pins and this capacitor.

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