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enter image description here

I want to use a diode switch to drain a capacitor. The switch in the circuit is opened and closed regularly. The op-amp will flip between ground potential and 5V at its output. When the output is low, the capacitor gets drained through D1. Do I need R2 and if so, how do I calculate its value based on the op-amp (and diode?) characteristics? Does it simply depend on the maximum output current of the op-amp, so if e.g. the maximum is 50 mA, I'll use a 100 Ohm resistor for R2?

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    \$\begingroup\$ You haven't mentioned why you want to drain it and thus how you need it to happen. Obviously the higher the value of R2, the longer it will take to discharge the capacitor. \$\endgroup\$ – TooTea May 11 at 11:23
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    \$\begingroup\$ 1/2W 100 ohms will work , and OA will get hot when 5V is applied but why? \$\endgroup\$ – Tony Stewart EE75 May 11 at 11:37
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    \$\begingroup\$ As Tony says, whenever SW1 is closed, the opamp will be sinking whatever R2 allows almost all the time (depending on the duty cycle of V1, which you haven't mentioned). Permitted steady state power dissipation of the op-amp might well be an important design constraint then. \$\endgroup\$ – TooTea May 11 at 11:55
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    \$\begingroup\$ Please add more details regarding the voltage sources. Is the input actually 100 Hz? How long does the switch remain closed, connecting the other voltage source to the capacitor, while the input signal is present? \$\endgroup\$ – devnull May 11 at 11:55
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    \$\begingroup\$ Wait, are you saying that your sample/hold circuit can charge the capacitor, but it can't discharge it? Why is that? \$\endgroup\$ – Dave Tweed May 11 at 12:09
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I just wanted to point out two small things about your current approach, that probably you already noticed:

  • The maximum current you can sink is limited by the opamp
  • The minimum voltage you can discharge the capacitor down to, is limited by the forward voltage of the diode
  • The continuous power rating of the current limiting resistor must not be exceeded

As for resistor value, you have some limits that you have to ensure:

Limiting the current of the opamp: $$R>\dfrac{V_{CAP}(0)-V_D}{I_{MAX}}$$

Ensuring that the resistor is not operating out of spec $$R\ge\dfrac{V_{CAP,RMS}²}{P_{RATED}} = \dfrac{-2t}{C\cdot \ln\left(1-\dfrac{2tP_{RATED}}{V_{CAP,0}²\cdot C}\right)}$$

Ensuring that the capacitor is discharged before the beginning of the next cycle $$R\le-\dfrac{t}{C\cdot \ln(V_D/V_{CAP,0})}$$

Where:

  • \$P_{RATED}\$ is the continuous pulsed power rating of the resistor
  • \$t\$ is the length of each discharging cycle
  • \$V_{CAP,0}\$ is the maximum / initial charge of the capacitor
  • \$V_D\$ is the forward voltage of the diode

Try to select a resistor which fulfills all requirements above and it should cover the most critical cases.

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  • \$\begingroup\$ Great, thanks a lot for the detailed reply! These constraints are just what I was hoping to find here. \$\endgroup\$ – one_three_three_seven May 11 at 20:46
  • \$\begingroup\$ @one_three_three_seven I fixed the second constraint. The denominator signs were flipped. \$\endgroup\$ – vtolentino May 12 at 14:39
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This is what I gathered from your comments, additionally to what is stated in the question:

  • I need to discharge it to roughly 0.5V in less than about 20 ms

  • The capacitor [...] I need it to be at least 1 µF to keep the output smooth

  • The V1 params [...] a trigger signal that sends a short (about 20 ms) pulse every few seconds at most

  • SW1 exists, but it's a multiplexer IC. [...] remains closed for 1 ms every 40 ms.

For these conditions, the MCP602 datasheet indicates that the IC will not be damaged by the discharge current even if no limiting resistor is used:

enter image description here

Simulating a similar op. amp. regarding the output limits (LT1677), just as an illustration, with resistors from practically zero to 1 k (10 values per decade), it is clear that as the value goes below 100 Ohm, the discharge time is basically limited by the output current of the op. amp.

enter image description here

Considering that the capacitor holds \$125 \mu J\$, even if your op. amp. dissipates 10 times this energy, due to internal currents, at each second, power dissipation is clearly not a concern.

But you may want to limit the initial current for other reasons, e. g. avoiding the short bursts periodically at the power rails. For that, a combination of a current limiting resistor within your timing constraints with some smoothing at the input may be in order.

enter image description here

enter image description here

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    \$\begingroup\$ Perfect, just what I was looking for. Thanks so much for taking the time to put this together! The smoothing capacitor before the OA is a great idea. \$\endgroup\$ – one_three_three_seven May 11 at 20:43
  • \$\begingroup\$ How did you get those graphs? with simulation? what kind of software did you use? \$\endgroup\$ – John Cortex May 12 at 15:00
  • \$\begingroup\$ @JohnCortex the graphs come from simulating the above circuit in LTSpice: analog.com/en/design-center/design-tools-and-calculators/… \$\endgroup\$ – devnull May 12 at 15:25
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In terms of peak discharge current, the worst case is if the opamp output stage can swing all the way down to 0.00 V. Two things: a) it can't; b) if it could, there would be zero power dissipated in the output stage. But for this discussion, lets assume the output can swing down to 0 V, and yet still possibly overheat.

To make things worse, lets assume that D1 haw a forward voltage drop of 0 V. Now, 100% of the capacitor voltage will appear across R2. For a 100 ohm resistor, this is a peak current of 50 mA and a peak power dissipation of 0.25 W. But ...

That is the case only for a microsecond. As the capacitor discharges, the voltage across the resistor decreases, decreasing the power dissipated in the resistor, the diode, and the opamp output stage. In 3 milliseconds (three time constants = 3 x R2 x C1), the voltage across C1 is only 5% of its initial value.

In the real world, by this time the current through R2 probably is 0 V, because a) the opamp output stage cannot swing down to 0.0 V; and b) D1 has a forward voltage (Vf) of somewhere around 0.2-0.3 V. So there will be an energy spike when the node 1 goes low, but it will be so short that it will not affect R2 or OA1.

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  • \$\begingroup\$ +1, and it is mentioned that discharge will happen at "every few seconds at most". Even if it was 100 times per second and all capacitor energy went to the resistor, it would dissipate 12.5 mW on average. \$\endgroup\$ – devnull May 12 at 15:59

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