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I am using a 3v3 logic level (VCC in schematic) to switch low-current 12v power for a remote sensor (SPWR). The switch is to power down the sensor when not in use to save power. Even with the sensor removed, so that SPWR is open circuit, the MOSFET does magic smoke and dies. I can't fathom what's going on here.

The MOSFET is "P Trench 30V 4A 1.3V @ 250uA 44 m? @ 4.3A,10V SOT-23-3L": https://datasheet.lcsc.com/szlcsc/Alpha-Omega-Semicon-AOS-AO3401A_C15127.pdf

The NPN transistor is an S8050: https://datasheet.lcsc.com/szlcsc/Changjiang-Electronics-Tech-CJ-S8050_C2146.pdf

enter image description here

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    \$\begingroup\$ Are you sure you have the correct pin out for the FET? Applying -12V across the gate-source shouldn’t cause any problems \$\endgroup\$
    – Frog
    May 11, 2021 at 20:01
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    \$\begingroup\$ I am not sure. But I do notice that you are right at the absolute maximum gate-to-source voltage. That is not a good design. You might want to use less than 12V or find a transistor with Vgs(max) of 20V. Or add a zener diode in series with the collector of Q1. Are you able to tell whether the transistor fails during turn on or turn off? That could be a clue. \$\endgroup\$
    – mkeith
    May 11, 2021 at 20:03
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    \$\begingroup\$ I'm with mkeith. When using a PMOS on the high side and pulling the gate straight to GND, the limiting factor is not the Vds max. It is the Vgs max which is always considerably lower. \$\endgroup\$
    – DKNguyen
    May 11, 2021 at 20:03
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    \$\begingroup\$ Oh hang on; 12V is absolute maximum for the gate voltage. Perhaps put an extra resistor between the gate and the collector of Q1, around 150R will reduce the gate voltage to 10V, you could probably use a lower voltage than that depending on the load current. BTW your resistor values are quite low, you could make them all 10 times larger and save a bit of power, since you don’t need really high switching speed. \$\endgroup\$
    – Frog
    May 11, 2021 at 20:05
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    \$\begingroup\$ Breadboard is full of parasitic capacitance and inductance; FET was likely oscillating. \$\endgroup\$
    – rdtsc
    May 11, 2021 at 20:31

1 Answer 1

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You're at the limit of gate-source voltage (Vgs). You can reduce this by adding a series resistor between the NPN collector and the FET gate.

Make R37 10k, and add the second 10k. Then the gate will swing between +12V (Vgs = 0V) and +6V (Vgs = -6V). Then the FET should be happy.

Try it (simulate it here):

enter image description here

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  • \$\begingroup\$ A simple way to gain a feature is place a LED between the gate and transistor collector. Pick your favorite color it should work. Stay with your existing resistors, they will work just fine. \$\endgroup\$
    – Gil
    May 12, 2021 at 3:59

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