As a way to improve my meagre FPGA skills, I'm moving some of my retrocomputing projects to purely FPGA implementations in VHDL, where each individual chips have the exact signals interface as they had in the old times. While having a lot of fun, I find that my exotic designs are not exactly what the FPGA manufacturers had in mind when producing chips and toolchains, and I don't get much help from their documentation. I'm intentionally asking a couple of questions together, as I suspect not many people will be interested in distinct detailed answers on the subject.
One of my next designs is a simulated retro DRAM chip (such as the 4164) using some block RAM. How can I duplicate the exact delays for the availability of data after asserting /RAS and /CAS? I found out that the VHDL "after" and "wait" statements are to be used only in test benches, as they are not synthetizable. So what could be the most efficient wait to do that? Should I add an additional high-frequency clock and an internal counter, so as to simulate an asynchronous chip by being internally synchronous? Could I use some kind of delay loop? Something else? As I don't have enough problems yet, I added this additional constraint: I don't want to use any "IP" inside a given simulated chip.
The other side of my quest is about clocks, a subjet I'm not really familiar with. Some of my favourite chips, such as the 68000, perform operations on the falling edge of their clock (e.g. 68000 states S1 and S7). When I learned the basics of FPGA design, I've seen a lot of scary warnings about using both the rising and falling edges in the same design. So how can I simulate such signals? For other chips, such as the 6809, there are sometimes two clocks, one leading the other (Q and E). Is it "safe" to use a PLL and happily drive a single simulated design with two clocks having a slightly distinct phase?
Bonus: I understand that both Vivado and Quartus have the ability to specify timing constraints and perform timing analysis of the designs. I never used them before, as I'm still learning and my main tool is still the waveform viewer. Could those tools be abused so as to assist me when I'm creating original retro-like designs connected to simulated retro components with timing constraints?