99% of the watches uses a 32768kHz crystal with a suitable divider (i.e. 15 bits for a 1Hz final clock).
How do they do the centisecond? Dithered counters. If you, for example, divide by 2 and on the next cycle divide by 4 the net result is one third of the frequency. With a suitable state machine for sequencing the dividers you can obtain any wanted ratio. Of course duty cycle and jitter are the most horrible things seen on this planet but who cares?
As for the display refresh rate, you have two frequency to handle: the segment clock (needed for the LCD to not burn off) and the commons duty (used to multiplex the 'digits', if there is a common for each digit, for example). The whole frame cycle is a full sequence of common drives. In short, it can be whatever is a compromise between contrast, flicker and power consumption. In ULP microcontrollers (like the MSP430) often you even low the refresh while the display is 'idle' and raise it when there's something interesting to see. I suppose that 32Hz and 64Hz would be popular choices (for obvious reasons).