I'd like to be able to estimate gate counts of different designs for the purpose of architectural exploration. Below is what I found out. Please feel free to correct, comment, expand.

Logic gates

Two input NAND (NAND2) = 4 T(ransistors) = 1 gate

NOT = 2 T = 0.5 gates

Two input AND = NAND2 + NOT = 1.5 gates ?

N inputs NAND = 2*N T = N/2 gates ? Max reasonable N ?

XOR = 4 gates

Half adder = 5 gates

Full adder = 9 gates


MUX 2 :1 = 4 gates or 3 NAND2 + NOT = 3.5 gates ?

Multiple input muxes can be built from MUX2_1 or with multiple input NANDs (see above)

If anyone has some more data points for MUX 4:1, 8:1, 16:1, etc

Mux 2:1 with transmission gates = 4 T = 1 gate

How do I extend this to multiple input muxes ? What's the trade off with gate muxes ?

From this discussion, muxes tend to be transmission gate.

Flip-Flops (FFs)

Synchronous D FF = 6 gates

Enabled, synchronous D FF = D FF + MUX2_1 = 6 + 4 = 10 gates, 6 + 1 (transmission gate mux) = 7 gates, 6 + gated clock = 7 gates ? Which one is more common ?


RAMs made with D FFs => 7-10 gates/bit + suitable muxes (see above).

RAMs cell = 6T/bit = 1.5 gates/bit, dual port = 8T = 2 gates/bit

Now, this is the important part for me. From the above, RAM cells seem so much better but I remember a friend of mine telling me years ago, for a 256x8 RAM that "it wasn't worth it, might as well doing it with FFs".

I assume that there's some overhead here. In my designs I often consider small memories such as 64x8 or 128x16 and I'd really like to understand when one method is better than another. Some simple rule such as "when the number of bits is < then...", "when the depth is <, then...." etc.

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    \$\begingroup\$ The issue is mostly dependant on the underlying cell library… for FPGAs for example almost everything is mapped to LUTs and FF have certain built-in tricks. Also RAM has many different implementations (included pseudostatic ones) \$\endgroup\$ Commented May 13, 2021 at 6:02

2 Answers 2


Building half gates from a NAND gate considering its transistor count is not always correct, from the next picture [Boylestad, Nashelsky (1992) Electronic devices & applications] you can see that there is only one transistor and four diodes. Thus I bet that the digital design of logic elements is more extensive (consider also FET's which may have different configurations). enter image description here

Similarly with flip flops, muxes and so much other devices. Indeed nand gates are the building block of digital electronics, because from them you can bassically design every other device, but the design normally changes and may be simplified or enlarged depending on the application, wheather it is for power, communications, data storage, etc.

Finally, as you said a RAM can be build form D FF's, but once again, the main difference between building one by yourself and usign an Integrated Circuit, is that the IC has been previously designed for an application in frecuency, power, simplicity, price, etc. whereas the one you build by yourself will be more personal and you will have to do the math on its performance, complexity and bulkiness.

I hope this has been helpful. Greetings.

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    \$\begingroup\$ But the overwhelming majority of digital logic designs are CMOS now. The circuit you show was an antique when it was published almost 30 years ago. I'm sorry, but I don't think this circuit is at all relevant. \$\endgroup\$ Commented May 13, 2021 at 12:21

if you meant to design using CMOS/FinFET technology then what you mentioned is absolutely correct. when you want to design any memory be it SRAM or DRAM we can use either a cross-coupled inverter or use D FFs. but what to use is completely the designer's choice. there is no hard and fast rule. the major consideration is the leakage power and speed when it comes to SRAM or any memory. if your design includes all the considerations then you can use anything be it D FFs or Cross-Coupled inverters.

Coming to muxes, one can make n:1 mux depending on the requirement. the major consideration would be power consumption and delay. as there will be a lot of gates in the mux the power consumption and delay may increase. there are many techniques for the reduction of power consumption, you can search the articles/papers from IEEE.

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    \$\begingroup\$ I guess I was looking for a way to estimate the overhead for RAM cell SRAM vs FFs memories. Otherwise 1.5 gates/bits vs. 7-10 gates/bits is no contest, at least as far as area is concerned. \$\endgroup\$
    – ozne
    Commented May 13, 2021 at 7:07

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