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A usual datasheet rating for maximum allowed input current into opamps is 10 mA. Initially I thought that this is some kind of DC limit of what the clamping diodes could handle before thermal destruction. I thought that this can be exceeded if the fault is short e.g. a few ms.

However then I learned that silicon latch-up could be the issue if the input current (and thus voltage) reaches a critical level even momentarily.

But during ESD the input current can be much higher without causing permanent damage. At least this is what I assume if opamps claim an ESD rating in their datasheet.

So the question is: can the input current be exceeded for transients? And if so for what approximate duration?

Edit: I am specifically interested in bipolar and JFET input opamps. And in precision application where a series resistor is sometimes not an option.

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If the 10mA rating is 'absolute maximum' you not only should not exceed it, you should not even get close to it.

ESD rating is generally for the chip not powered. If it is powered when the ESD strike happens, then other damage can occur.

There are other failure modes than thermal, and continuous current that the chip is not designed for can have deleterious effects over time (especially at elevated temperatures).

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  • \$\begingroup\$ So 1 minute with 5 mA is safer than 1 ns with 20mA? I am trying to get an understanding at which timescale this rating is relevant \$\endgroup\$
    – tobalt
    May 13, 2021 at 21:55
  • \$\begingroup\$ There are different failure modes so you can't really say one is safer than the other. 1 minute at 5mA is within ratings and is not very long in comparison to device lifetime. 20mA pulsed with the device powered might cause it to fail from latchup. \$\endgroup\$ May 13, 2021 at 21:57
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There are many types of catastrophic failure mechanisms.

Fusing a sub-micron sized gold wirebond or damaging a tiny fast ESD diode that is current-limited with 2 stages can happen in xxx milliseconds with excessive energy. Normally the dissipation of a standard test with a 4kV 100 pF HBM finger model pulse is slowed down with 10k R current limiting and diode capacitance and resistance when conducting. Yet on the good conductive surface ESD can discharge in picoseconds. The ESD diodes must also be faster than the CMOS it is protecting.

  • The failure mechanisms depend greatly on the energy level.[J] This is also how fuses are defined. E= Cold R * I^2t rating.

  • The max current limits (with no time factor) depend on thermal damage (self-heating and cooling).

  • A small signal diode may conduct hundreds of milliamps but as we know junction capacitance increases with size and that reduces the diode's ability to conduct faster than an ESD pulse. So they are made exceptionally small but cascaded in 2 stages to attenuate the voltage. Originally all CMOS and linear ESD could only tolerate 5mA steady due to self-heating. Now many IC's specify 10 mA with some improvements in the diode's RC time constant with technology.

I believe this is the reason for your observation of an absolute max of 10mA.

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  • \$\begingroup\$ Thanks for this. Just to be clear because you mention CMOS. What if the opamp is not a CMOS type but a standard bipolar or JFET? What changes? \$\endgroup\$
    – tobalt
    May 14, 2021 at 13:03
  • \$\begingroup\$ the thresholds of damage or Abs. Max specs may be different , that's all \$\endgroup\$ May 14, 2021 at 13:06

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