555 timer won't trigger monostable mode unless I add a switch between R12 and ground?

Question

I have this setup which is a part of a bigger circuit to control motors.

This is supposed to be a timer in monostable mode with about a minute of hi output when triggered.

The lines going down are to give the Q2 base high and Q4 to turn the timer off when the downward lines are high but when they are low the timer should trigger and start giving out high.

I tried randomly to put a switch between R12 and ground and that helped trigger the device. So I would in theory turn the device on and then turn on the button to trigger this timer.

I don't quite understand why it won't trigger when this bottom common line is low.

Should it be dragging the base of Q2PNP down to open it which would then add voltage to the base of Q3 NPN which would drag the trigger of the timer down?

The setup of the C2 and R2 is so that the output time won't be affected by the input staying low so the output time is always the same as this capacitor and resistor pulls it up.

I want it to just

• Device ON
• Trigger low
• Output Hi
• until trigger is reset by Q4 or time is up.

Am I missing something here?

---------EDIT----------

Uploading the full schematic just for a better understanding.

Currently, the rest of the schematic works fine in simulation except the part I posted originally.

I have a counter to count button clicks.

Once a button clicks a 555 timer for backwards goes high, and once it drops from high to low it triggers the 555 timer for turning.

Both backwards and turning timers give out high into the forward 555 timer to make sure that one isnt giving out high.

I just need the forward timer to start off as high and get deactivated by the other timers but once they go back to low that forward will be activated once again.

Using a PNP transistor as a switch is a mess and a half.

I just realized that the whole point of C2 and R2 was for the trigger event to only trigger once so it wouldn't affect the output time, but on this specific timer the output is allowed to be high as long as it can.

Answer 1

There are several things wrong with the large schematic. Let's start with U1, the 4017 counter.

1. The clock input. There is not switch debouncing, so the number of counts with each button press will be erratic. by itself, R10 does nothing and could be deleted. OR, you can connect the switch directly to pin 14, connect R10 from pin 14 to GND, and add a capacitor from pin 14 to GND. Now R10 will be part of a debouncing network. To start, try 100K and 0.22 uF. If there still are erroneous counts, increase the capacitor rather than the resistor.

2. The Reset input. My guess is that R1-C1 are supposed to differentiate the reset signal coming from U2 pin 3. If so, this is not a good way to do that. The problem is that there is no DC path from the Reset input to either rail, so it will float between input pulses. This is a serious problem for CMOS logic inputs, and can lead to device failure in some cases. Also, if C1 stays charged, a U2 pin 3 output might be completely ignored.

If the intent is to turn that signal into a 20 ms reset pulse, do this: Delete D1. Disconnect the top of R1 from the left side of C1, and connect it directly to pin 15. Leave C1 in series between the U2 output and Reset input. Now whenever U2pin3 goes high, a short, clearly defined pulse will appear at the Reset input. To keep U2 from working so hard, shift the R1-C1 values by 100x, to 100 K and 0.22 uF; same pulse width, way less U2 output current. If this circuit is in a high noise environment, compromise with 10 K and 2.2 uF.

Next, the U2 circuit.

3. Delete D3. This actually is working against you, because it prevents U1 pin 10 (output 4) from turning off Q1 quickly and cleanly. It also makes the circuit more susceptible to noise.

4. Increase R11 to 10 K. A 4017 output can supply only about 4 mA. Increasing the base resistor will relieve stress on the pin 10 output stage withing affecting the rest of the U2 circuit in any way. Also, 12 mA base current is pretty high for a small signal transistor.

5. What is the purpose of R5 and C3?

6. R6 is unnecessarily small, and this low value means it is dissipating almost 150 mW when Q1 is on. Increasing it to 10 K will not affect the rest of the circuit.

The U4 circuit.

7. Again, there is no pull-down resistance from the Q11 base to GND. Because of the diode-ORing ainto R21, add a 10 K resistor from the Q11 base to GND.

8. Increase R21. As above, this will decrease the Q11 base current to a safer level.

9. The way the circuit is drawn, the first three button presses will result in only one triggering of U4. U1 is not a normal counter. In fact, internally it is a shift register with lots of gating to create the stepped outputs. There is no guarantee than each 4017 output will go low before the next output goes high, so the first three button presses after a reset might be seen as one long trigger pulse.

10. As above, what is the purpose of R17 and C8?

All for now. later, I'll update this response with more items.

Answer 2

The pulse at the Trigger input is only 100 us. Does it really need to be so short? Consider increasing R2, R3, and R4 to 10 K.

There needs to be a pull-down resistor from the base of Q3 to GND. This assures a complete and rapid turn-off when Q2 turns off.

The circuit will not trigger under any circumstances with the components shown. Please edit the schematic to show the input signal that is supposed to cause a trigger event. What are the characteristics of that signal (voltage, frequency, rise time, current drive capability, etc.)?

Answer 3

There are 3 series diodes between the outputs of U2, U4, U5 and R12 (Don't forget D6, D13 & D21). This means that the Vbe of Q2 will never fall below about 0.7 V and Q2 & Q3 will never turn off.

Add an extra diode in series with D4 & D5 to ensure Q2 & Q3 switch off when the output of U2, U4 or U5 go high.