the image below is supposed to represent the last segment of the circuit, where the 'updown' input would change the direction of the counting: when updown=0 it counts backwards (f,e,d,...1,0,f...) when =1, it counts upwards (0,1,2,...e,f,0...) enter image description here

yet i am even strugling to design one with two bits. i have tried different variations of the circuit below but none seem to work the way it has to enter image description here

note that i am only allowed to use j-k flip-flops (74LS112) and XNOR gates (TTL 74266)

could someone give me a hint or something because i am in severe pain

  • 1
    \$\begingroup\$ We won't do your homework for you but we can give you hints. Start by creating a state transition table. Use that to create K-maps or truth tables for each of the J and K inputs. Take it at least that far, and show us your work. Then let us know if you have a specific question. \$\endgroup\$ – Elliot Alderson May 16 at 19:15
  • \$\begingroup\$ i reworked it and have came to the conclusion that (x= updown input) j3=k3=xq2q1q0+x'q2'q1'q0' , j2=k2=xq1q0+x'q1'q0' , j1=k1=xq0+x'q0', j0=k0=1. turns out i cant simplify these function any further tho. any ideas? ill keep working on it of course \$\endgroup\$ – peter griffin May 16 at 22:54
  • \$\begingroup\$ The two-bit circuit you show is not asynchronous, it is synchronous. \$\endgroup\$ – the busybee May 17 at 6:21
  • \$\begingroup\$ Its possible to make any of the other standard logic gates (AND, NAND, OR, NOR, NOT, XOR) from just XNOR gates. Therefore, if you can make something out of those other gates, then you can certainly make it out of XNOR gates. \$\endgroup\$ – user4574 May 17 at 14:53

You're thinking too much. You don't have to use any sophisticated techniques for logic synthesis. It's not only possible to make the counter, it's very simple.

BTW, If the "last" stage is the most significant stage, and CLK is the signal being counted, there's no answer. All the less significant stages would need a faster clock, from somewhere. "Last" must mean the least significant stage.

Another hint (looking for another anonymous down vote): the answer isn't a counter whose next count is the current count minus 1 when the direction command changes from up to down, or to the current count plus 1 when the command changes from down to up. The giveaway is the given "last" stage. When the direction command changes it toggles the LSB before seeing the next clock pulse. The answer, then, only has to be a counter that changes from being an up counter to a down counter, or vice-versa, but not very smoothly.



Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Not the answer you're looking for? Browse other questions tagged or ask your own question.