I've to design a firmware for an embedded device which may be in different error conditions at the same time. Each error condition requires to set the hardware components of the system into different states. Means every error condition requires a dedicated transition callback function for entering the error sub-state or a dedicated "in state" logic which is executed simultaneously with potential other error sub-state logic. In addition the states of the HW system components may be conflicting in different error conditions. Means there is need for prioritization to resolve potential conflicts between "safe states" for different error conditions. Each error condition shall be acknowledge-able. Means each error sub-state requires explicit transition callback function for leaving the error sub-state.
How should I model this design using e.g. an UML state diagram?
BTW: I've designed UML state diagrams before. However I never had to deal with that kind of requiremenst before. In my opinion the requirements cannot be abstracted in an "off the shelf" state machine design like I used before. The question is not about UML state diagrams but the given requirements.