I have a circuit that calls for one open collector buffer for driving a shared line (/WAIT via Zilog Z80) and one typical AND gate. I've consolidated these into a single 74LS09 open collector quad 2-input AND gate IC.
To make the "typical" AND gate behave typically, I assumed something in the range of 10K to 1K would suffice for a pull-up resistance, but my tests are telling me something else. My oscilloscope sees a rise time of 2.4 microseconds at 10K, and 250nS at 1K. If I cut it down to 320 it still takes 92nS of rise time.
Referring to: https://www.ti.com/lit/ds/sdls034/sdls034.pdf I was surprised to see the rise time TPLH on page 4 with 2K resistance should be around 35nS. The best I have achieved is around 500nS. In comparison, the fall time I've measured is around 17nS and hasn't changed much between tests.
As you've probably detected, I'm not incredibly familiar with this domain. Does anyone know what knowledge I may be missing? If there is more context I can add about the test circuit please let me know.
- My unused inputs are all tied low
- My LS09 will be used in a circuit that is clocked at 1MHz, so it needs to be a bit snappy
- All logic is at 5V
- Adding 10pF of capacitance to output against 5V or ground did not impact results
- Decreasing input rise time did not impact results
- These LS09 chips were bought on Amazon (https://www.amazon.com/gp/product/B08CCD472L), and were shipped in an antistat bag
- Multiple LS09 chips respond the same way, although all are from the same seller