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I have a custom board with a new platform which does not have any tool to configure the DDR setup( I asked). I have the Source code for the uboot.config (CONFIG_DDR.c, CONFIG_DDR.h etc). So I have to manually find the correct values to start the Linux Kernel. I have the original Uboot-file EMR EMR2 ZQPROG etc

The platform consist of NOR-flash, eMMC, DDR3 and the CPU (with integrated DDR-controller)

I can run the Uboot and upload the OS to the eMMC through a serial interface and ethernet (TFTP). But when it(eMMC) is trying to upload the OS to RAM it fails. I guess it has to do with the setup of the DDR3 different parameters. I have tried to modify the Impedance levels and DDR-clock, but without results. Right now it stops at:


Starting kernel ...

[    3.949129] blk_update_request: I/O error, dev mmcblk0, sector 0 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
[    4.483700] blk_update_request: I/O error, dev mmcblk0, sector 1 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
[    5.018260] blk_update_request: I/O error, dev mmcblk0, sector 2 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
[    5.552826] blk_update_request: I/O error, dev mmcblk0, sector 3 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
[    6.087385] blk_update_request: I/O error, dev mmcblk0, sector 4 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
[    6.621942] blk_update_request: I/O error, dev mmcblk0, sector 5 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
[    7.156531] blk_update_request: I/O error, dev mmcblk0, sector 6 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
[    7.691104] blk_update_request: I/O error, dev mmcblk0, sector 7 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
[    7.701324] Buffer I/O error on dev mmcblk0, logical block 0, async page read
[    9.281759] blk_update_request: I/O error, dev mmcblk0, sector 0 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
[    9.816328] blk_update_request: I/O error, dev mmcblk0, sector 1 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
[   10.350884] blk_update_request: I/O error, dev mmcblk0, sector 2 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
[   10.885446] blk_update_request: I/O error, dev mmcblk0, sector 3 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
[   11.420005] blk_update_request: I/O error, dev mmcblk0, sector 4 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
[   11.954561] blk_update_request: I/O error, dev mmcblk0, sector 5 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
[   12.489121] blk_update_request: I/O error, dev mmcblk0, sector 6 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
[   13.023675] blk_update_request: I/O error, dev mmcblk0, sector 7 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
[   13.033900] Buffer I/O error on dev mmcblk0, logical block 0, async page read
00:00:16 Timeout. Device /dev/mmcblk0p1 not found
00:00:16
00:00:16 Devices found:
    .
    ..
    mmcblk0boot0
    mmcblk0boot1
    mmcblk0
    ubi_ctrl
    i2c-155
    i2c-154
    i2c-153
    i2c-152
    i2c[   16.357555] reboot: Restarting system

Do you have any suggestions on how to proceed (I am really stuck) or any suggestions on a generic(free) DDR software?

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  • \$\begingroup\$ These parameters are specific to the DDR3 part , you should reach out to the CPU or DDR3 vendor to obtain this information. \$\endgroup\$
    – crasic
    Commented May 18, 2021 at 15:39
  • \$\begingroup\$ Most, if not all, of the timing parameters should be listed in the datasheet of the DDR chip. If there isn't one, I wouldn't use that part. \$\endgroup\$
    – Aaron
    Commented May 18, 2021 at 15:50
  • \$\begingroup\$ @Aaron this is not the case for DDR3 devices, part of the config is board/layout specific, requiring timing test in situ (eye diagrams while adjusting params) so at least the board vendor should be responsible. For high speed memory Vendor solicitation and also NDA is , unfortunately, the normal process in the industry. Some may choose to publish the timing config, especially for a "mass market device" but this is not usually the case for DDR3, more common for DDR. \$\endgroup\$
    – crasic
    Commented May 18, 2021 at 15:53
  • \$\begingroup\$ @crasic Got it. I missed the 3, just saw the letters DDR. I've only done DDR, so I had a datasheet. \$\endgroup\$
    – Aaron
    Commented May 18, 2021 at 15:58
  • \$\begingroup\$ Thank you for good discussion! \$\endgroup\$
    – Aard
    Commented May 18, 2021 at 16:11

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