I am designing standard cells at the transistor level and I want the characterize these cells into a library file (.lib). Do I need to define the delay, power and constraint templates (sequential) compulsorily?
Can I not just start off with setting the PVT values? I am using Cadence Liberate for characterization. I used Cadence Virtuoso for transistor level designing and now I have the post layout netlist spice (.sp) files.
thanks in advance!