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I am given the equation for parasitic-capacitance as:

\$ C = \dfrac{\epsilon_r \cdot \epsilon_0 \cdot L \cdot W }{ d }\$

I am also told my trace is to be 1000 micrometers long (1mm) and 45nm wide. The spacing between traces is 45nm as well (and the thickness of the metal layer is 45nm). A second coplanar trace is 100 micrometers long (.1mm).

I am not sure what I am plugging into the equation. I understand that the adjacent trace will distort the signal on my original trace with noise, especially at high power or high frequency, which I assume is the point, but I need to calculate the actual capacitance. I don't mind doing the math, but I need to know what goes where in the equation.

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    \$\begingroup\$ Just to be sure, are you interested in the capacitance between the trace and a ground or power plane below it, or the capacitance between two traces next to each other? \$\endgroup\$
    – The Photon
    Jan 30, 2013 at 18:26

4 Answers 4

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Your equation:

\$ C = \frac{e_oe_rLW}{d} \$

Is the parallel plate capacitance equation and assumes that the plate size L*W is large enough and the gap size d is small enough that most of the e-field is captured between the plates. With your system, most of the capacitance will be in the field lines around the wires so the result will not be accurate.

Usually this would be simulated with software but as a first approximation you should use the capacitance of a two wire line. This will be some what inaccurate because teh conductors are a significant size wrt to the spacing. But it will be better.

\$ C = \frac{2 \pi e_r e_o L}{2 ln(2h/b)} \$

where h = 1/2 the distance between wires and b = the "radius" of the wires.

In your case the wires will not be circular (but they are not square either). but this is a good first approx..

Some open source software, that is kind of hard to use if you don't have the right tools is found by a search of "fast field solvers"

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An estimate of what the value could be:

parasitic capacitance, I found this at TI site: "http://www.ti.com/lit/an/sloa013a/sloa013a.pdf"

“Circuit traces on a PCB with a ground and power plane will have about 1−3 pF/in and interconnecting wires have about 20−30 pF/ft conductor to shield or ground”.

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As others have noted, it can be quite hard to approximate capacitance from physical layouts due to fringing effects.

This answer: adjacent trace capacitance (horizontal) provides a formula for strips of equal length, but since one of your strips is a factor 10 longer than the other strip, it will be a poor approximation in your case.

I have developed a tool to simplify calculation of capacitance for multilayer PCBs: http://www.capext.com

The software, CapExt, is commercial, but I am more than happy to provide free evaluation licenses.

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    \$\begingroup\$ Commercials/ product promotion are not appreciated to be present. But, always accepted to have the information in profile data \$\endgroup\$
    – User323693
    Jan 7, 2017 at 13:03
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Some better approximation of two wires: http://www.pulsedpower.eu/toolbox/toolbox_capacitances.html#capacitances

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  • \$\begingroup\$ As a link my become dead in the future the answer can lose its content. That's why it is recommended to copy the relevant part, useful information into the answer and keep the link as reference. \$\endgroup\$ Nov 28, 2016 at 16:29

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