0
\$\begingroup\$

I'm very curious about why the 3T APS píxel sensor implements an NMOS reset transistor. As it is well-known, we will have a voltage of Vdd-Vth during the reset phase. This situation will imply higher FPN, thus the initial integration voltage will be highly dependent on Vth. If we replaced it with a PMOS transistor, we always would be reset to Vdd.

enter image description here

\$\endgroup\$
1
  • 1
    \$\begingroup\$ Although beneficial for image lag reduction, the use of PMOS instead of NMOS doubles the reset noise power. To reconcile the image lag and low-power requirements, 6T-cell solutions exist, combining hard and soft resets. \$\endgroup\$
    – V.V.T
    May 19, 2021 at 8:58

1 Answer 1

1
\$\begingroup\$

Although beneficial for image lag reduction, the use of PMOS instead of NMOS doubles the reset noise power. To reconcile the image lag and low-power requirements, 6T-cell solutions exist, combining hard and soft resets.

\$\endgroup\$

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service and acknowledge you have read our privacy policy.

Not the answer you're looking for? Browse other questions tagged or ask your own question.