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I am using S32K142 64-pin Microcontroller. 3V3 Supply.

I am interfacing this Stepper Motor Driver to the Microcontroller using SPI lines.

I have already asked a similar question over here

The SDO pin from the Driver IC is the output and Microcontroller takes this signal as the input.

The SDO pin is a push-pull output. And this is connected to the GPIO pin of the Microcontroller.

I am trying to understand on how much current would flow (source or sink) from the push-pull output to the Microcontroller input pin (sourcing current or sinking current). Like, on what parameter is the current dependent upon?

Like, does it depend on the internal pull-up or pull-down resistor of the microcontroller? Should I enable the internal pull-up or pull-down resistor?

I am doing this because, I am trying to make a logic IO compatibility between the Driver IC and the Microcontroller.

Since the Microcontroller takes input from the SDO pin, I have not mentioned Voh and Vol levels under the Microcontroller column. And similarly, since the SDO pin is output from the Driver IC, I have not mentioned the values for its Vih and Vil.

enter image description here

So, can someone tell me how to find the Voh and Vol voltage of the SDO pin on the Driver IC?

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  • \$\begingroup\$ You are asking the wrong question from a DC point of view, There is no pullup/down required. The drivers are active pullup/down controlled by std. CMOS FET RdsOn \$\endgroup\$
    – D.A.S.
    Commented May 19, 2021 at 10:32

2 Answers 2

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The stepper motor driver gives you a pull-up and a pull-down resistance measured with a 5 mA current (either sinking or sourcing).

The output is pulled to VSDO or GND respectively.

With this you can calculate the output high level: \$V_{OH} = V_{SDO} - (75\ \Omega * 5\ \text{mA}) = V_{SDO} - 0.375\ \text{V}\$

But that is for a 5 mA load. Your controller pin as input has a maximum input leakage current of only 5 µA. So there will be a negligible voltage drop.

There is no minimum load specification for SDO, so you don't need to enable an internal pull-up or pull-down resistor.

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  • \$\begingroup\$ Thank you very much for the answer. So, since the Input leakage current of my input port in the microcontroller is 5uA, the Voh level will be Vsdo - (75ohm * 5uA) = Vsdo - 375uV. Am I correct? So, in that case, Voh will be almost equal to Vsdo which is 3.3V. Am I correct? \$\endgroup\$
    – user220456
    Commented May 19, 2021 at 10:26
  • \$\begingroup\$ CMOS input is typically >> 10M worst case 1M , so not the problem from 50 ohm source, that's not even close to being an issue. Concern is with mismatched impedances on long cables at high data rates. CMOS will only draw 5mA or more when Ic=CdV/dt from input capacitance \$\endgroup\$
    – D.A.S.
    Commented May 19, 2021 at 10:28
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    \$\begingroup\$ @Newbie yes, from a DC point of view. Tony is making a good point about impedance mismatch for longer traces. At which point a trace becomes "long" depends on the communication frequency. \$\endgroup\$
    – Arsenal
    Commented May 19, 2021 at 10:48
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The stepper IC has an SDO support that allows 3.3V interface with standard 5.5V logic impedances. Historically this CMOS push-pull impedance for 5.5V logic has always been 50 ohms +/-50% and this IC is within this boundary at 5V.

  • It will be slightly higher than typical at a lower supply voltage of 3.3V.
  • When operating at the maximum possible data rate for the longest possible cable such as 200 (STP) ~ 240 ohm (UTP) twisted pair, damped edges can be achieved by adding 150 Ohms to the SDO driver Tx to reduce the impedance mismatch which improves data rate or signal integrity and reduces crosstalk as it filters excess bandwidth, associated with mismatch ringing. (alternatively one could use 50 ohm coax.)

The uC input threshold is near Vdd/2 with recommended limits shown in your question are fine as the load current is always determined by the Rx leakage current (uA) and device input and parasitic capacitance. (Ic=CdV/dt) (No problem)

You do not have any DC current loading problems whatsoever.

The concern is for impedance matching on long cables.

Simulation

enter image description here

Same cct at lower SDO clock rate 100kHz on 10m cable enter image description here

Scope shows direct drive switched to add 150 ohms after mid-stream for comparison of reflections and improved noise immunity.

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  • \$\begingroup\$ Thank you for the information. But the connection between the SDO output and the microcontroller is just a trace. Not a cable. So, in that case, would this be a cause of concern? \$\endgroup\$
    – user220456
    Commented May 19, 2021 at 10:38
  • \$\begingroup\$ NO since the delay time of 5ps/cm is far shorter than signal rise time \$\endgroup\$
    – D.A.S.
    Commented May 19, 2021 at 10:46
  • \$\begingroup\$ you are basically asking how does CMOS logic work? How do I read datasheets? What causes signal integrity issues. When is it a non-issue? CMOS input never draws 5mA for a steady-state level !!! \$\endgroup\$
    – D.A.S.
    Commented May 19, 2021 at 10:47
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    \$\begingroup\$ correction 50 ps/cm while 50 ohms into e.g. one 10pF load is 500 ps rise time, \$\endgroup\$
    – D.A.S.
    Commented May 19, 2021 at 11:13
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    \$\begingroup\$ you can compute trace C[pF] from Z and length or Saturn PCB.exe \$\endgroup\$
    – D.A.S.
    Commented May 19, 2021 at 11:15

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