How to ignore simulation only ports when mapping to FPGA pins?

A design has a number of simulation ports that should not be tied to FPGA pins.

A VHDL example is shown in the source below, where the sim_only_* ports are for simulation only, thus should not be mapped to FPGA pins.

entity mdl is
port(
-- FPGA pins
clk_i : in  std_logic;
rst_i : in  std_logic;
a_i   : in  std_logic;
z_o   : out std_logic;
-- Simulation pins only
sim_only_in  : in  std_logic := '0';
sim_only_out : out std_logic);
end entity;


The sim_only_* pins can be safely left unused by Quartus, since the inputs have default value.

When running Quartus, the mapper tries to map the sim_only_* ports to unused FPGA pins, which is not desired.

How can I specify that Quartus should just ignore the sim_only_* ports on the VHDL design?

• Edit the SDC file, remove all lines that mapped these pins. – Mitu Raj May 20 at 5:56
• Does this answer your question: Setting FPGA pins as virtual? – megasplash May 20 at 8:17
• @MituRaj: There are no mapping of the simulation pins only, but the problem is that Quartus does a default mapping of unused ports to free FPGA pin. However, the unused simulation ports only should be ignored instead. – EquipDev May 20 at 10:53
• @megasplash: Thanks, that is the solution :-) If you care to write an answer, I will upvote and select it. Otherwise, I will write an answer myself in a couple of days, so others can have the information available here at StackOverflow. – EquipDev May 20 at 10:54
• Verilog has compiler directives that are useful for this sort of thing. Using these, you can have 2 sections of code: one of which is used for simulation and one for synthesis. For obvious reasons, you don't want to lean too heavily on this technique. VHDL has pragmas, but I don't have direct experience with VHDL. (ifdef etc). – Troutdog May 27 at 15:12

Making a pin virtual can be done via Assignment Editor (Ctrl+Shift+A`) like this: