A design has a number of simulation ports that should not be tied to FPGA pins.

A VHDL example is shown in the source below, where the sim_only_* ports are for simulation only, thus should not be mapped to FPGA pins.

entity mdl is
    -- FPGA pins
    clk_i : in  std_logic;
    rst_i : in  std_logic;
    a_i   : in  std_logic;
    z_o   : out std_logic;
    -- Simulation pins only
    sim_only_in  : in  std_logic := '0';
    sim_only_out : out std_logic);
end entity;

The sim_only_* pins can be safely left unused by Quartus, since the inputs have default value.

When running Quartus, the mapper tries to map the sim_only_* ports to unused FPGA pins, which is not desired.

How can I specify that Quartus should just ignore the sim_only_* ports on the VHDL design?

  • \$\begingroup\$ Edit the SDC file, remove all lines that mapped these pins. \$\endgroup\$
    – Mitu Raj
    Commented May 20, 2021 at 5:56
  • 2
    \$\begingroup\$ Does this answer your question: Setting FPGA pins as virtual? \$\endgroup\$
    – megasplash
    Commented May 20, 2021 at 8:17
  • \$\begingroup\$ @MituRaj: There are no mapping of the simulation pins only, but the problem is that Quartus does a default mapping of unused ports to free FPGA pin. However, the unused simulation ports only should be ignored instead. \$\endgroup\$
    – EquipDev
    Commented May 20, 2021 at 10:53
  • \$\begingroup\$ @megasplash: Thanks, that is the solution :-) If you care to write an answer, I will upvote and select it. Otherwise, I will write an answer myself in a couple of days, so others can have the information available here at StackOverflow. \$\endgroup\$
    – EquipDev
    Commented May 20, 2021 at 10:54
  • \$\begingroup\$ Verilog has compiler directives that are useful for this sort of thing. Using these, you can have 2 sections of code: one of which is used for simulation and one for synthesis. For obvious reasons, you don't want to lean too heavily on this technique. VHDL has pragmas, but I don't have direct experience with VHDL. (`ifdef etc). \$\endgroup\$
    – Troutdog
    Commented May 27, 2021 at 15:12

1 Answer 1


There is a useful option to use a Virtual Pin assignment. It is often used when compiling a design with a number of pins that exceeds the available physical pin count of a target device. For example, this can be useful to make preliminary estimations for some module, which is only a part of a whole design.

Making a pin virtual can be done via Assignment Editor (Ctrl+Shift+A) like this:

Virtual pin assignment

[Assignment] Specifies whether an I/O element in a lower-level design entity can be temporarily mapped to a logic element and not to a pin during compilation. The virtual pin is then implemented as a LUT. This option should be specified only for I/O elements that become nodes when imported to the top-level design.

Here is a related video on Using Virtual Pins from Intel FPGA website.


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