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I am setting up a fast I2C communication between a microcontroller (STM32, master) and an FPGA (Zynq-7000, slave). Currently, it won't work correctly because whenever the FPGA pulls down SDA, it causes some interference on positive clock pulse of pulse of SCL. This results in the FPGA detecting clock edges whenever it pulls down SDA and the clock pulse is positive. See the picture below.

enter image description here

I tried to solve this problem by making the wire shorter and by adding a capacitor between SDA and ground. It works better now, but it still won't work always since there is still a little interference. See the picture below.

enter image description here

Do you know of an easy solution to decrease the interference even more? I tried adding a larger capacitor, but this results in the SDA becoming to slow, and therefore, it will not be detected in time. I cannot make the wire any shorter than the current length.

The I2C communication operates on 3.3 V and the frequency of SCL is 400 kHz. The I2C lines are pulled up at the microcontroller side with 1 kΩ resistors I cannot replace there resistors, but I can add some if necessarry. The wire is a 28 AWG ribbon cable with length of 50 cm (20 inch).

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    \$\begingroup\$ Use interleaved ground wires or STP cable instead, reduce R value in half \$\endgroup\$ May 21, 2021 at 15:22
  • \$\begingroup\$ Or less than half. Make the interleaved grounds connected at ONE END ONLY (master) \$\endgroup\$ May 21, 2021 at 16:01
  • \$\begingroup\$ @TonyStewartEE75 I know that's the recommendation for a shield but I thought grounds used as reference/return paths were to be connected on both sides, can you elaborate? \$\endgroup\$
    – DamienD
    May 21, 2021 at 16:30
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    \$\begingroup\$ What is the pin mapping of the SDA and SCL in the cable? Are they adjacent wires, or are the there grounds between SDA and SCL? If properly designed, I2C can go many meters (well maybe not at 400kHz but at least HDMI, DVI and VGA cables have I2C in them and these cables come in several meters in length). \$\endgroup\$
    – Justme
    May 21, 2021 at 18:41
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    \$\begingroup\$ Can you show a picture and pinout of the cable? \$\endgroup\$
    – bobflux
    May 22, 2021 at 10:12

3 Answers 3

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The easiest solution is to slow down the edges. Reduce the drive strength of the FPGA's pins. Add a larger capacitor. If that makes the signals too slow for 400 kHz, reduce the frequency. (Then, reduce the frequency even further and increase the capacitor even more, to get more safety margin.)

Increase the distance between the two signals, i.e., put a ground line between them. This will probably require a larger cable. (It is common to have every second line in a ribbon cable be ground.)

It might make sense to use an entirely different protocol, such as LVDS.

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Slowing down the edge rates will help, maybe a few tens of ohms in series with the pins at the FPGA?

The other thing you can do is implement digital filtering on the FPGA side, if you have a fast FPGA internal clock that you are reclocking the I2C bus to (fairly standard) you can do things like have a short shift register and only change the internal state of a signal once all the bits in the shift register are '1' or '0', this deglitches the inputs.

Grounding matters, especially on that cable.

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You are generating a large impedance mismatch with your pull up resistors. The values should be the same for both devices on the same voltage rail. For 400 khz you want to use about 4.7k-22k this will likely resolve your issue. I recommend removing the pull up resistors from the boards and using your own.

Alternatively you may add resistors in series with the lines to reduce current flow. The parasitic inductance of a standard PTH 1/4 resistor will improve those really high speed edges. Adding small amounts of additional inductance maybe say 10 nH and a nano farad or two to form a LC filter is about the best you can do.

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