6
\$\begingroup\$

I want to set up an LED display, and I'm looking at using a bunch of 16-bit LED driver chips (like TI TLC5927) to run a 16x16 LED matrix. Then I'd like to maybe put a few of these 16x16 displays together to make a bigger display. Since they are chainable, that should work in principle.

The problem as I see it is distributing the CLK, LATCH, and OE signals, as they aren't redriven by the chips. And I'm thinking the wimpy little Arduino output isn't going to drive much more than 20 or 30 chips before the signals become too blurry to be considered digital anymore.

So... is the solution to just put a 74HCT125 buffer every so many chips to re-drive the CLK, LATCH, and OE signals? Any pitfalls with that approach? Maybe I'm just overthinking it.

\$\endgroup\$
  • 1
    \$\begingroup\$ Similar question: electronics.stackexchange.com/questions/40242/… I've use Schmitt-trigger buffers, as Steven suggested in his answer and it worked well, at least for 16 registers chained on a distance of about 10 m \$\endgroup\$ – m.Alin Jan 31 '13 at 7:52
  • \$\begingroup\$ I've seen 74HCT125 used as a buffer for SPI lines in several commercial LED boards \$\endgroup\$ – miceuz Jan 31 '13 at 13:30
4
\$\begingroup\$

As long as the signals are all driven by a single source, which they are in your case, your solution will work. These signals usually do need very little current, though. For a small number of ICs, you should be fine without. For 20-30, yes, buffer. Also note that the many ICs will introduce a small propagation delay in your data line. This will at worst require you to also delay your clock etc. to compensate for the possibility of clock reaching before the data does if you operate at very high frequency.

| improve this answer | |
\$\endgroup\$
  • \$\begingroup\$ Yea, I'll probably run it with an Arduino, so I don't think I'll be running the clock no faster than 2MHz :-) \$\endgroup\$ – vicatcu Jan 31 '13 at 17:20
  • \$\begingroup\$ For the sake of completeness, at 2 MHz clock period is 500ns, which means data is set up 250ns before clock transistion. Even assuming that zero stabilization time is sufficient (as in, data becoming available just before or at the time of the clock transition. Usually, you need some set up / stabilization time), and assuming that you use one buffer per shift resistor for the sake of simplicity in calculation, that means for 25 chained registers you can have a maximum propagation difference, ie, shift register propagation time minus that of the buffer should be less than 10ns. Thats tight. \$\endgroup\$ – Chintalagiri Shashank Jan 31 '13 at 17:39
  • \$\begingroup\$ Thanks for the additions, I would probably not use a buffer per shift register, that seems like overkill... and anyway, the 74HC125 has a propagation delay on the order of 10ns. I would probably just put a redrive buffer every 5 or 10 shift registers. And if there were problems, slow down the clock a bit :) \$\endgroup\$ – vicatcu Jan 31 '13 at 20:15
  • \$\begingroup\$ You misunderstand. Putting a buffer per shift register makes the situation better, since each buffer compensates for the delay introduced by its corresponding shift register. If you have one per ten, then one buffer has to compensate for the delay of ten shift resgisters. The shift register will likely have more delay per IC, most likely, and what is important is the delay between the two signal chains, not the independent delay. But you get the picture now anyway. Best of luck :) \$\endgroup\$ – Chintalagiri Shashank Jan 31 '13 at 20:50

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Not the answer you're looking for? Browse other questions tagged or ask your own question.