AXI Stream Master - M_AXIS_TVALID not always be '1' during a transaction and M_AXIS_TLAST

Question

I am implementing my AXI Stream Master module which can be use with Vivado DMA module. The connection of module is shown:

I have 3 questions:

1.) Could the "m_axis_tvalid" signal be non continuous at '1' during the stream transaction? Because some calculation delay might occur in the "axis_top_test_0" module, so the the m_axis_tdata might not be provided continuously. The provided reference only gives some simple condition. I have written my testbench signal which is shown below, so that you can understand my question in a better way:

2.) Is it necessary to set the "m_axis_tlast" to '1' when my transaction is finished? I test the xilinx sdk provided program xaxidma_example_simple_poll.c and it always stops at this line272:

while ((XAxiDma_Busy(&AxiDma,XAXIDMA_DEVICE_TO_DMA)) ||
    (XAxiDma_Busy(&AxiDma,XAXIDMA_DMA_TO_DEVICE))) {
        /* Wait */
}

Then, the program cannot be ended. When I rerun the program again, I can see that the data is transferred to the Rx already (which is the result of the 1st run of the program). Does it mean that the AxiDma is always busy when custom module asserts m_axis_tvalid to '1', if the dma does not receive m_axis_tlast = '1', then the dma will always be busy?

3.) Let's come back to the 1st question, I tested the implementation in question 1, and I still get the result of question 2. So, the only way to resolve it is to first store all my calculation results in a buffer, then I trigger the m_axis transaction once?

Answer 1

I get the answer from here and would like to write a short summary.

1.) The signal M_AXIS_TVALID can be discontinuous, so this testbench is valid (I have tested it on the hardware by setting some interrupt signal to influence the M_AXIS_TVALID):

2.) M_AXIS_TLAST is to tell the AXI S2MM DMA that a transaction is done. So, the XAxiDma_SimpleTransfer can be run properly and XAxiDma_Busy(&AxiDma,XAXIDMA_DEVICE_TO_DMA) is not always busy which is set to zero.

3.) (2) has resolved this problem. Moreover, I made a mistake of transferring false MAX_PKT_LEN at the line259 of XAxiDma_SimpleTransfer. This is also a factor that will make the program stuck at this line272-XAxiDma_Busy.