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I am new to implementing boolean expressions in CMOS form, and I understand that the "C" in CMOS stands for "Complementary", so it is an inverter circuit.

What I don't understand is: All the tutorials say that if you want to design an "AND" gate you have to place the transistors in series if they are nMOS and in parallel if they are pMOS. Why is that?

Why can't we just say "for AND gate: place the nMOS in parallel and the pMOS in series" so that we'll be able to implement the functions directly, without need of an inverter before the output?

Would that create some problem that I haven't come across yet?

I had a CMOS full adder circuit that I had to extract the boolean expression from, and I noticed that the expression I was extracting was correct according to the aforementioned implementation rules, but then I noticed the inverter before the output, and got confused. Is there some logical reason for the rules being like this?

EDIT: In below picture, the OR operation in nMOS corresponds to placing the transistors in parallel. The opposite is true for pMOS. My question is, why did we have to implement the inverse function? Couldn't we have made the circuit directly, using the original function and inverting the "rules" about OR corresponding to nMOS in parallel (making them "nMOS corresponds to nMOS in series" instead)?

function implemented is !Z. Why not directly Z?

(link of video where i got the above screenshot:https://www.youtube.com/watch?v=7XEUB_dTaK0)

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    \$\begingroup\$ A schematic is better than words. You can add one in using the CircuitLab button on the editor toolbar. Double-click a component to edit its properties. 'R' = rotate, 'H' = horizontal flip. 'V' = vertical flip. Note that when you use the CircuitLab button on the editor toolbar and "Save and Insert" on the editor an editable schematic is saved in your post. That makes it easy for us to copy and edit in our answers. You don't need a CircuitLab account, no screengrabs, no image uploads, no background grid. \$\endgroup\$
    – Transistor
    May 24, 2021 at 19:12
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    \$\begingroup\$ Why can't we say "for AND gate: place the nMOS in parallel and the pMOS in series" so that we'll be able to implement the functions directly, without need of an inverter before the output? ----- NO, because that won't be \$A.B\$, it will be \$ A'. B'\$ instead. Draw and analyze .... \$\endgroup\$
    – Mitu Raj
    May 24, 2021 at 20:11
  • \$\begingroup\$ but we will have removed the inverter. Won't that make it A.B again? \$\endgroup\$
    – mltsd
    May 24, 2021 at 20:26
  • \$\begingroup\$ @mltsd I think you're too focused on the boolean algebra and are using mistaken ideas that are difficult to verify since it's in equation form. Sit down and draw a truth table of an AND or OR gate. Then swap parallel<->series and draw the truth table again. You should find that doing so changes the operation but the inversion of the inputs remain (at least that's what I found unless I made a mistake). \$\endgroup\$
    – DKNguyen
    May 24, 2021 at 21:06
  • \$\begingroup\$ @DKNguyen i have understood where i was getting confused. I was looking at nMOSFETs in series and translating that into an AND operation when it is a NAND. Must've seen that somewhere and gotten confused. \$\endgroup\$
    – mltsd
    May 24, 2021 at 21:09

3 Answers 3

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In CMOS (as in most logic families) we always want to avoid shorting the power supply to ground.

So, let's say you have a NAND gate that looks like this: enter image description here

We need to make sure that if the path from Z to ground is on then the path from Z to Vdd must be off.

So, in order for there to be a path from Z to ground, both N1 and N2 must be ON. For that to happen, both A and B must be HIGH. But if both A and B are high, then P1 and P2 are both cut-off. So, no path through them.

We also need to make sure that if the path from Z to Vdd is on, then the path from Z to ground must be off.

So, for there to be a path from Z to Vdd, either P1 or P2 must be on. For that, either A or B (or both) must be LOW. If A is low, then N2 is cut-off. If B is low, then N1 is cut-off.


As the earlier answer suggested, the "complementary" in CMOS refers to the devices. But in fact, in static gates, the pull-up (P device) and pull-down (N device) sub circuits must be complementary.

The rule is: Given a pulldown circuit described by a series-parallel network: a) For any two nodes separated by two devices in series, transform the sub circuit into the same two nodes connected by two devices in parallel. b) For any two nodes separated by two devices in parallel, transform the sub circuit into the same two nodes connected by two devices in series.

So the P network is always the series/parallel "dual" of the N network. That will ensure that no matter what input combination arrives, the stack will never short power and ground.

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  • \$\begingroup\$ Thanks, my main point of confusion was some people placing nMOS transistors in series and saying that that was an AND operation. I see now that in CMOS we are working with NANDs and NORs. \$\endgroup\$
    – mltsd
    May 24, 2021 at 21:04
  • \$\begingroup\$ Ahhh.... They weren't wrong. They were using AND in the sense that the pulldown equation was A AND B. There is a certain consistency in this. \$\endgroup\$ May 25, 2021 at 22:33
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Complementary does not mean there is an inverter circuit.

Complementary means, there are both NMOS and PMOS transistors, as logic that existed before CMOS had only NMOS transistors.

In a CMOS circuit, NMOS transistors are able to pull strongly low, and PMOS transistors are able to pull strongly high.

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  • \$\begingroup\$ Thanks, I had misinterpreted the meaning of the word \$\endgroup\$
    – mltsd
    May 24, 2021 at 19:32
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The "complementary" in CMOS refers to the field-effect transistor fabrication process that uses complementary and symmetrical pairs of p-type and n-type MOSFETs for logic functions. (This is instead of all p-type or all n-type transistors.)

If you can post a schematic of your series and parallel circuits we can address those too.

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