2
\$\begingroup\$

In PCI Express (PCIe) a completion packet is to be generated for both memory read and IO read.

A Byte Count field is part of the completion packet, and for a memory read (MRd) in the simple case, this field simply indicates the number of returned bytes.

However, for IO read (IORd) the "PCI Express Base Specification Revision 2.1" specifies in section "2.2.9. Completion Rules" that "... For all other types of Completions, the Byte Count field must be 4.". So, even through IO read request can be of size 1, 2 or 4 byte, the spec. says that the completion packet Byte Count field should be 4.

When doing simulation on an Altera/Intel FPGA, I have some indication that this special casing of the Byte Count field value for IO read is not correct, through it is difficult to determine if it is a simulation only problem.

Is the spec. right about this special casing of Byte Count field value for IO read?

\$\endgroup\$
1
\$\begingroup\$

Well, the spec seems pretty clear about that, and it's the spec so by definition the spec is right and therefore the simulation is wrong.

Also, I think the special case is actually memory reads where the byte enables are actually considered. For other completions, it's simply the length field times 4.

\$\endgroup\$

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Not the answer you're looking for? Browse other questions tagged or ask your own question.