I know that chemical vapor deposition (CVD) is a vacuum deposition method used to produce high-quality, high-performance solid materials. The process is often used in the manufacture of semiconductors to produce thin films, there are several CVD methods, such as LPCVD, PECVD etc. These methods can be used to deposit a thin film on the substrate controllable with process parameters such as temperature, pressure, and precursor gases.

My question

Why is CVD not used to deposit gate oxides in the manufacture of NMOS devices?

I can't find the reasons and the main causes.

  • \$\begingroup\$ Just checking...you're saying oxide is NOT used despite still being called a gate oxide? \$\endgroup\$
    – DKNguyen
    Commented May 25, 2021 at 20:41
  • \$\begingroup\$ @DKNguyen Why is oxide not used in the CVD process in the manufacture of door oxide in the NMOS device? sorry, I didn't express myself well \$\endgroup\$
    – LUFER
    Commented May 25, 2021 at 21:08
  • 1
    \$\begingroup\$ maybe it's easier to heat the thing in an oxygen atmosphere than to deposit "oxide" vapour? \$\endgroup\$
    – user16324
    Commented May 25, 2021 at 21:34

2 Answers 2


CVD is used for modern gate dielectrics.

The simple answer is it is much easier to thermally oxidize silicon to get a high quality gate dielectric than it is to deposit one. Therefore, you use oxidization of silicon for gate diectrics whenever you can. Additionally, most CVD techniques deposit too quickly to precisely control the handful-of-nm thick gate dielectrics used in modern CMOS. But, current state of the art CMOS does in fact use CVD gate dielectrics.

CVD (chemical vapor deposition) is a class of thin film deposition methods. Most of which are too fast, produce too low of a material quality, or are otherwise difficult to precisely control, to use for depositing a gate dielectric. One of the deposition methods under the CVD umbrella is ALD (atomic layer deposition). Using ALD you can precisely control the thickness of a deposited film by depositing a single atomic layer of material at a time. This is used in modern CMOS gate dielectrics, usually to deposit a hafnium based oxide. This allows us to use materials with much higher dielectric constants than you get with silica.

  • \$\begingroup\$ During this period of research I only found contradictions. Your explanation is excellent, thank you very much. But as I said, I'm having a contradiction in the research, I found it, but I'm not sure about it. A: SiO2 is a refractory material that is not easy to vaporize. In short: some say they can use oxide, but others say they are unable to use it. I can't find the explanation. Why is it not used in the fabrication of NMOS gate oxides in the CVD method? \$\endgroup\$
    – LUFER
    Commented Jun 1, 2021 at 18:24
  • \$\begingroup\$ @LUFER Can you clarify what you mean by "oxide"? The normal definition would be something along the lines of "an oxygen containing compound" are you using it to mean SiO2 specifically? Do you know what CVD is? You dont vaporize the source material. The source is already a gas, often multiple gasses, and usually a fairly complex molecule, but its not a solid chunk of whatever it is you want to deposit. That would be PVD. \$\endgroup\$
    – Matt
    Commented Jun 1, 2021 at 18:28
  • \$\begingroup\$ @LUFER Anyway, thermally grown SiO2 is very high quality. CVD SiO2 is pretty terrible quality. If you try very hard you can make it an okay material, but not great. But once you give up thermal oxidation and move to CVD you have a wide range of materials available. HfO2 based gate dielectrics allow you to have much better gate control than you would have with SiO2, so there is no reason to use SiO2 most of the tine. \$\endgroup\$
    – Matt
    Commented Jun 1, 2021 at 18:34

The gate oxide is grown from the silicon wafer, not deposited on top. This provides a very good interface between the gate oxide and the silicon. For MOS devices the current flows right at this interface, and any imperfections will reduce the mobility of the carriers.

After the gate oxide is grown and the gate polysilicon is patterned, the source/drain regions will be implanted through the thin oxide. There will probably be an anneal step to heal any damage from the ion implant step, but after that we don't want to use any high temperatures. High temperature processing will cause the implanted elements to diffuse, and we lose the sharp channel edges we got from using the polysilicon as a mask.

So, after implantation the field oxide and any intermetal oxides will be deposited at (relatively) low temperatures.


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