I'm creating an RF connection between a PSoC4 BLE device and the cypress MIFA antenna according to this app note.

I'm confused about the pads that are required by the components used in the RF matching network. Using a grounded co-planar waveguide with 50 Ohm impedance trace, I've calculated a particular trace width and ground plane separation.

However, when the component pads contact the trace, the pads are a different size than the rest of the trace. So I suspect there will be an impedance change there, causing reflections and problems. There are at least 4 such pads along the length of the trace with a pi-filter methodology.

Looking at the PSoC BLE Design files, the pads for the matching network components are sized to match the thickness of the trace precisely.

RF Pads

The manufacturer datasheet for one of the caps used (C14, bridges the gap in the trace, in-line cap Johanson Technology Inc. 500R07S1R5BV4T) does not provide a recommended land pattern. However, the width of the package is spec'd at 0.02". This is quite different than the trace width that I currently have calculated (0.012") for my waveguide.

So, to check my thinking: given that I have a CPWG, that means I can vary both the trace width and the co-planar ground plane clearance to control my impedance. So should I resolve this difference by setting the trace width to 0.02", and then setting the ground plane clearance to get 50 ohms? If so, I guess that means I have make sure all of components use the same size pad?


The most common approach is to design your microstrip or CPWG to match the component pads for devices in the path. For 0402 components, that means 20 mil trace, as you mentioned. And, yes, this means generally using all 0402 components for that RF path.

If you use narrower trace (12 mil) with 20 mil pads, you will have unwanted parasitic capacitance at each pad location. Depending on the frequency of operation, this may or may not be a problem. Frankly, for BT at 2.4GHz, this may not be much of an issue. Still, why settle for less than the best you can do if you are designing the PCB?


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